drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c

100

DPU_REG_WRITE(c, CDM_CDWN2_COEFF_COSITE_H_1,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c

102

DPU_REG_WRITE(c, CDM_CDWN2_COEFF_COSITE_H_2,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c

108

DPU_REG_WRITE(c, CDM_CDWN2_COEFF_OFFSITE_H_0,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c

110

DPU_REG_WRITE(c, CDM_CDWN2_COEFF_OFFSITE_H_1,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c

112

DPU_REG_WRITE(c, CDM_CDWN2_COEFF_OFFSITE_H_2,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c

138

DPU_REG_WRITE(c,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c

146

DPU_REG_WRITE(c,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c

163

DPU_REG_WRITE(c, CDM_CDWN2_OUT_SIZE, out_size);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c

164

DPU_REG_WRITE(c, CDM_CDWN2_OP_MODE, opmode);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c

165

DPU_REG_WRITE(c, CDM_CDWN2_CLAMP_OUT, ((0x3FF << 16) | 0x0));

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c

202

DPU_REG_WRITE(c, CDM_CSC_10_OPMODE, csc);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c

203

DPU_REG_WRITE(c, CDM_HDMI_PACK_OP_MODE, opmode);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c

224

DPU_REG_WRITE(c, CDM_MUX, mux_cfg);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c

98

DPU_REG_WRITE(c, CDM_CDWN2_COEFF_COSITE_H_0,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

110

DPU_REG_WRITE(&ctx->hw, CTL_PREPARE, 0x1);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

147

DPU_REG_WRITE(&ctx->hw, CTL_MERGE_3D_FLUSH,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

150

DPU_REG_WRITE(&ctx->hw, CTL_INTF_FLUSH,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

153

DPU_REG_WRITE(&ctx->hw, CTL_WB_FLUSH,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

156

DPU_REG_WRITE(&ctx->hw, CTL_CWB_FLUSH,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

162

DPU_REG_WRITE(&ctx->hw,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

168

DPU_REG_WRITE(&ctx->hw, CTL_PERIPH_FLUSH,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

172

DPU_REG_WRITE(&ctx->hw, CTL_DSC_FLUSH,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

176

DPU_REG_WRITE(&ctx->hw, CTL_CDM_FLUSH,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

179

DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

186

DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

439

DPU_REG_WRITE(c, CTL_SW_RESET, 0x1);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

473

DPU_REG_WRITE(c, CTL_LAYER(mixer_id), 0);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

474

DPU_REG_WRITE(c, CTL_LAYER_EXT(mixer_id), 0);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

475

DPU_REG_WRITE(c, CTL_LAYER_EXT2(mixer_id), 0);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

476

DPU_REG_WRITE(c, CTL_LAYER_EXT3(mixer_id), 0);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

479

DPU_REG_WRITE(c, CTL_FETCH_PIPE_ACTIVE, 0);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

561

DPU_REG_WRITE(c, CTL_LAYER(lm), mixercfg[0]);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

562

DPU_REG_WRITE(c, CTL_LAYER_EXT(lm), mixercfg[1]);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

563

DPU_REG_WRITE(c, CTL_LAYER_EXT2(lm), mixercfg[2]);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

564

DPU_REG_WRITE(c, CTL_LAYER_EXT3(lm), mixercfg[3]);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

566

DPU_REG_WRITE(c, CTL_LAYER_EXT4(lm), mixercfg[4]);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

612

DPU_REG_WRITE(c, CTL_TOP, mode_sel);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

613

DPU_REG_WRITE(c, CTL_INTF_ACTIVE, intf_active);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

614

DPU_REG_WRITE(c, CTL_WB_ACTIVE, wb_active);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

615

DPU_REG_WRITE(c, CTL_CWB_ACTIVE, cwb_active);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

616

DPU_REG_WRITE(c, CTL_DSC_ACTIVE, dsc_active);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

617

DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, merge_3d_active);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

620

DPU_REG_WRITE(c, CTL_INTF_MASTER, BIT(cfg->intf_master - INTF_0));

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

623

DPU_REG_WRITE(c, CTL_CDM_ACTIVE, cfg->cdm);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

656

DPU_REG_WRITE(c, CTL_TOP, intf_cfg);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

682

DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

701

DPU_REG_WRITE(c, CTL_INTF_ACTIVE, intf_active);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

708

DPU_REG_WRITE(c, CTL_INTF_MASTER, 0);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

715

DPU_REG_WRITE(c, CTL_CWB_ACTIVE, cwb_active);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

721

DPU_REG_WRITE(c, CTL_WB_ACTIVE, wb_active);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

727

DPU_REG_WRITE(c, CTL_DSC_ACTIVE, dsc_active);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

733

DPU_REG_WRITE(c, CTL_CDM_ACTIVE, cdm_active);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

751

DPU_REG_WRITE(&ctx->hw, CTL_FETCH_PIPE_ACTIVE, val);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

768

DPU_REG_WRITE(&ctx->hw, CTL_PIPE_ACTIVE, val);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

785

DPU_REG_WRITE(&ctx->hw, CTL_LAYER_ACTIVE, val);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

98

DPU_REG_WRITE(&ctx->hw, CTL_START, 0x1);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cwb.c

44

DPU_REG_WRITE(c, CWB_MUX, cwb_mux_cfg);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cwb.c

45

DPU_REG_WRITE(c, CWB_MODE, input);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

101

DPU_REG_WRITE(c, DSC_FIRST_LINE_BPG_OFFSET, data);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

105

DPU_REG_WRITE(c, DSC_BPG_OFFSET, data);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

109

DPU_REG_WRITE(c, DSC_DSC_OFFSET, data);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

115

DPU_REG_WRITE(c, DSC_FLATNESS, data);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

118

DPU_REG_WRITE(c, DSC_RC_MODEL_SIZE, data);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

125

DPU_REG_WRITE(c, DSC_RC, data);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

138

DPU_REG_WRITE(c, off, dsc->rc_buf_thresh[i]);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

144

DPU_REG_WRITE(c, off, rc[i].range_min_qp);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

150

DPU_REG_WRITE(c, off, rc[i].range_max_qp);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

156

DPU_REG_WRITE(c, off, rc[i].range_bpg_offset);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

181

DPU_REG_WRITE(c, dsc_ctl_offset, mux_cfg);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

42

DPU_REG_WRITE(c, DSC_COMMON_MODE, 0);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

57

DPU_REG_WRITE(c, DSC_COMMON_MODE, mode);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

74

DPU_REG_WRITE(c, DSC_ENC, data);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

78

DPU_REG_WRITE(c, DSC_PICTURE, data);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

82

DPU_REG_WRITE(c, DSC_SLICE, data);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

85

DPU_REG_WRITE(c, DSC_CHUNK_SIZE, data);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

89

DPU_REG_WRITE(c, DSC_DELAY, data);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

92

DPU_REG_WRITE(c, DSC_SCALE_INITIAL, data);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

95

DPU_REG_WRITE(c, DSC_SCALE_DEC_INTERVAL, data);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

98

DPU_REG_WRITE(c, DSC_SCALE_INC_INTERVAL, data);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

118

DPU_REG_WRITE(hw, DSC_CMN_MAIN_CNF, data);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

127

DPU_REG_WRITE(hw, sblk->enc.base + ENC_DF_CTRL, data);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

155

DPU_REG_WRITE(hw, sblk->enc.base + DSC_MAIN_CONF, data);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

160

DPU_REG_WRITE(hw, sblk->enc.base + DSC_PICTURE_SIZE, data);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

165

DPU_REG_WRITE(hw, sblk->enc.base + DSC_SLICE_SIZE, data);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

167

DPU_REG_WRITE(hw, sblk->enc.base + DSC_MISC_SIZE,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

173

DPU_REG_WRITE(hw, sblk->enc.base + DSC_HRD_DELAYS, data);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

175

DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_SCALE,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

181

DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_SCALE_INC_DEC, data);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

186

DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_OFFSETS_1, data);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

191

DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_OFFSETS_2, data);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

196

DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_OFFSETS_3, data);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

201

DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_OFFSETS_4, data);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

208

DPU_REG_WRITE(hw, sblk->enc.base + DSC_FLATNESS_QP, data);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

210

DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_MODEL_SIZE,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

219

DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_CONFIG, data);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

238

DPU_REG_WRITE(hw, sblk->ctl.base + DSC_CFG, data);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

262

DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_BUF_THRESH_0,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

267

DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_BUF_THRESH_1,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

272

DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_BUF_THRESH_2,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

277

DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_BUF_THRESH_3,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

288

DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_MIN_QP_0,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

294

DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_MAX_QP_0,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

300

DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_RANGE_BPG_OFFSETS_0,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

307

DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_MIN_QP_1,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

313

DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_MAX_QP_1,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

319

DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_RANGE_BPG_OFFSETS_1,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

326

DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_MIN_QP_2,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

332

DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_MAX_QP_2,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

338

DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_RANGE_BPG_OFFSETS_2,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

360

DPU_REG_WRITE(hw, sblk->ctl.base + DSC_CTL, mux_cfg);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

81

DPU_REG_WRITE(hw, sblk->ctl.base + DSC_CFG, 0);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

83

DPU_REG_WRITE(hw, sblk->enc.base + ENC_DF_CTRL, 0);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

84

DPU_REG_WRITE(hw, sblk->enc.base + DSC_MAIN_CONF, 0);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c

102

DPU_REG_WRITE(&ctx->hw, base + GC_C0_INDEX_OFF, 0);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c

103

DPU_REG_WRITE(&ctx->hw, base + GC_C1_INDEX_OFF, 0);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c

104

DPU_REG_WRITE(&ctx->hw, base + GC_C2_INDEX_OFF, 0);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c

107

DPU_REG_WRITE(&ctx->hw, base + GC_C0_OFF, gc_lut->c0[i]);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c

108

DPU_REG_WRITE(&ctx->hw, base + GC_C1_OFF, gc_lut->c1[i]);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c

109

DPU_REG_WRITE(&ctx->hw, base + GC_C2_OFF, gc_lut->c2[i]);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c

112

DPU_REG_WRITE(&ctx->hw, base + GC_LUT_SWAP_OFF, BIT(0));

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c

115

DPU_REG_WRITE(&ctx->hw, base, reg);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c

59

DPU_REG_WRITE(&ctx->hw, base, PCC_DIS);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c

63

DPU_REG_WRITE(&ctx->hw, base + PCC_RED_R_OFF, cfg->r.r);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c

64

DPU_REG_WRITE(&ctx->hw, base + PCC_RED_G_OFF, cfg->r.g);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c

65

DPU_REG_WRITE(&ctx->hw, base + PCC_RED_B_OFF, cfg->r.b);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c

67

DPU_REG_WRITE(&ctx->hw, base + PCC_GREEN_R_OFF, cfg->g.r);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c

68

DPU_REG_WRITE(&ctx->hw, base + PCC_GREEN_G_OFF, cfg->g.g);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c

69

DPU_REG_WRITE(&ctx->hw, base + PCC_GREEN_B_OFF, cfg->g.b);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c

71

DPU_REG_WRITE(&ctx->hw, base + PCC_BLUE_R_OFF, cfg->b.r);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c

72

DPU_REG_WRITE(&ctx->hw, base + PCC_BLUE_G_OFF, cfg->b.g);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c

73

DPU_REG_WRITE(&ctx->hw, base + PCC_BLUE_B_OFF, cfg->b.b);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c

75

DPU_REG_WRITE(&ctx->hw, base, PCC_EN);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c

98

DPU_REG_WRITE(&ctx->hw, base, GC_DIS);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

357

DPU_REG_WRITE(&intr->hw, intr->intr_set[reg_idx].clr_off,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

430

DPU_REG_WRITE(&intr->hw, reg->clr_off, DPU_IRQ_MASK(irq_idx));

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

432

DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

482

DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

484

DPU_REG_WRITE(&intr->hw, reg->clr_off, DPU_IRQ_MASK(irq_idx));

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

509

DPU_REG_WRITE(&intr->hw,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

527

DPU_REG_WRITE(&intr->hw,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

564

DPU_REG_WRITE(&intr->hw, intr->intr_set[reg_idx].clr_off,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

227

DPU_REG_WRITE(c, INTF_HSYNC_CTL, hsync_ctl);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

228

DPU_REG_WRITE(c, INTF_VSYNC_PERIOD_F0, vsync_period * hsync_period);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

229

DPU_REG_WRITE(c, INTF_VSYNC_PULSE_WIDTH_F0,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

231

DPU_REG_WRITE(c, INTF_DISPLAY_HCTL, display_hctl);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

232

DPU_REG_WRITE(c, INTF_DISPLAY_V_START_F0, display_v_start);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

233

DPU_REG_WRITE(c, INTF_DISPLAY_V_END_F0, display_v_end);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

234

DPU_REG_WRITE(c, INTF_ACTIVE_HCTL, active_hctl);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

235

DPU_REG_WRITE(c, INTF_ACTIVE_V_START_F0, active_v_start);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

236

DPU_REG_WRITE(c, INTF_ACTIVE_V_END_F0, active_v_end);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

237

DPU_REG_WRITE(c, INTF_BORDER_COLOR, p->border_clr);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

238

DPU_REG_WRITE(c, INTF_UNDERFLOW_COLOR, p->underflow_clr);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

239

DPU_REG_WRITE(c, INTF_HSYNC_SKEW, p->hsync_skew);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

240

DPU_REG_WRITE(c, INTF_POLARITY_CTL, polarity_ctl);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

241

DPU_REG_WRITE(c, INTF_FRAME_LINE_COUNT_EN, 0x3);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

242

DPU_REG_WRITE(c, INTF_CONFIG, intf_cfg);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

243

DPU_REG_WRITE(c, INTF_PANEL_FORMAT, panel_format);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

253

DPU_REG_WRITE(c, INTF_CONFIG2, intf_cfg2);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

254

DPU_REG_WRITE(c, INTF_DISPLAY_DATA_HCTL, display_data_hctl);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

255

DPU_REG_WRITE(c, INTF_ACTIVE_DATA_HCTL, active_data_hctl);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

265

DPU_REG_WRITE(c, INTF_TIMING_ENGINE_EN, enable != 0);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

283

DPU_REG_WRITE(c, INTF_PROG_FETCH_START,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

289

DPU_REG_WRITE(c, INTF_CONFIG, fetch_enable);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

307

DPU_REG_WRITE(c, INTF_MUX, mux_cfg);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

370

DPU_REG_WRITE(c, INTF_TEAR_SYNC_CONFIG_VSYNC, cfg);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

371

DPU_REG_WRITE(c, INTF_TEAR_SYNC_CONFIG_HEIGHT, te->sync_cfg_height);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

372

DPU_REG_WRITE(c, INTF_TEAR_VSYNC_INIT_VAL, te->vsync_init_val);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

373

DPU_REG_WRITE(c, INTF_TEAR_RD_PTR_IRQ, te->rd_ptr_irq);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

374

DPU_REG_WRITE(c, INTF_TEAR_START_POS, te->start_pos);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

375

DPU_REG_WRITE(c, INTF_TEAR_SYNC_THRESH,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

378

DPU_REG_WRITE(c, INTF_TEAR_SYNC_WRCOUNT,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

381

DPU_REG_WRITE(c, INTF_TEAR_TEAR_CHECK_EN, 1);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

399

DPU_REG_WRITE(c, INTF_TEAR_AUTOREFRESH_CONFIG, refresh_cfg);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

427

DPU_REG_WRITE(c, INTF_TEAR_TEAR_CHECK_EN, 0);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

448

DPU_REG_WRITE(c, INTF_TEAR_SYNC_CONFIG_VSYNC, cfg);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

491

DPU_REG_WRITE(c, INTF_TEAR_MDP_VSYNC_SEL, (cfg->vsync_source & 0xf));

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

513

DPU_REG_WRITE(c, INTF_WD_TIMER_0_LOAD_VALUE,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

516

DPU_REG_WRITE(c, INTF_WD_TIMER_0_CTL, BIT(0)); /* clear timer */

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

521

DPU_REG_WRITE(c, INTF_WD_TIMER_0_CTL2, reg);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

585

DPU_REG_WRITE(&intf->hw, INTF_CONFIG2, intf_cfg2);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c

109

DPU_REG_WRITE(c, LM_BORDER_COLOR_0_V12,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c

112

DPU_REG_WRITE(c, LM_BORDER_COLOR_1_V12,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c

143

DPU_REG_WRITE(c, LM_BLEND0_CONST_ALPHA + stage_off, const_alpha);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c

144

DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c

164

DPU_REG_WRITE(c, LM_BLEND0_CONST_ALPHA_V12 + stage_off, const_alpha);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c

165

DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c

181

DPU_REG_WRITE(c, LM_BLEND0_FG_ALPHA + stage_off, fg_alpha);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c

182

DPU_REG_WRITE(c, LM_BLEND0_BG_ALPHA + stage_off, bg_alpha);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c

183

DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c

197

DPU_REG_WRITE(c, LM_OP_MODE, op_mode);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c

222

DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, op_mode);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c

302

DPU_REG_WRITE(c, LM_BG_SRC_SEL_V12, LM_BG_SRC_SEL_V12_RESET_VALUE);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c

313

DPU_REG_WRITE(c, LM_BLEND0_FG_SRC_SEL_V12 + stage_off, value);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c

328

DPU_REG_WRITE(c, LM_BG_SRC_SEL_V12, LM_BG_SRC_SEL_V12_RESET_VALUE);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c

335

DPU_REG_WRITE(c, LM_BLEND0_FG_SRC_SEL_V12 + stage_off,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c

76

DPU_REG_WRITE(c, LM_OUT_SIZE, outsize);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c

83

DPU_REG_WRITE(c, LM_OP_MODE, op_mode);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c

93

DPU_REG_WRITE(c, LM_BORDER_COLOR_0,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c

96

DPU_REG_WRITE(c, LM_BORDER_COLOR_1,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c

28

DPU_REG_WRITE(c, MERGE_3D_MODE, 0);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c

29

DPU_REG_WRITE(c, MERGE_3D_MUX, 0);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c

32

DPU_REG_WRITE(c, MERGE_3D_MODE, data);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c

102

DPU_REG_WRITE(c, PP_SYNC_WRCOUNT,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c

105

DPU_REG_WRITE(c, PP_TEAR_CHECK_EN, 1);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c

113

DPU_REG_WRITE(&pp->hw, PP_AUTOREFRESH_CONFIG,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c

141

DPU_REG_WRITE(c, PP_TEAR_CHECK_EN, 0);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c

162

DPU_REG_WRITE(c, PP_SYNC_CONFIG_VSYNC, cfg);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c

264

DPU_REG_WRITE(c, PP_DSC_MODE, 1);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c

272

DPU_REG_WRITE(c, PP_DSC_MODE, 0);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c

282

DPU_REG_WRITE(pp_c, PP_DCE_DATA_OUT_SWAP, data);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c

56

DPU_REG_WRITE(c, base + PP_DITHER_EN, 0);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c

66

DPU_REG_WRITE(c, base + PP_DITHER_BITDEPTH, data);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c

73

DPU_REG_WRITE(c, base + PP_DITHER_MATRIX + i, data);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c

75

DPU_REG_WRITE(c, base + PP_DITHER_EN, 1);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c

94

DPU_REG_WRITE(c, PP_SYNC_CONFIG_VSYNC, cfg);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c

95

DPU_REG_WRITE(c, PP_SYNC_CONFIG_HEIGHT, te->sync_cfg_height);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c

96

DPU_REG_WRITE(c, PP_VSYNC_INIT_VAL, te->vsync_init_val);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c

97

DPU_REG_WRITE(c, PP_RD_PTR_IRQ, te->rd_ptr_irq);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c

98

DPU_REG_WRITE(c, PP_START_POS, te->start_pos);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c

99

DPU_REG_WRITE(c, PP_SYNC_THRESH,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

178

DPU_REG_WRITE(&ctx->hw, op_mode_off, mode_mask);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

198

DPU_REG_WRITE(&ctx->hw, sblk->scaler_blk.base + SSPP_VIG_OP_MODE, opmode);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

213

DPU_REG_WRITE(&ctx->hw, sblk->csc_blk.base + SSPP_VIG_CSC_10_OP_MODE, opmode);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

253

DPU_REG_WRITE(&ctx->hw, SSPP_FETCH_CONFIG,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

343

DPU_REG_WRITE(c, ubwc_ctrl_off, ctrl_val);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

364

DPU_REG_WRITE(c, format_off, src_format);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

365

DPU_REG_WRITE(c, unpack_pat_off, unpack);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

366

DPU_REG_WRITE(c, op_mode_off, opmode);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

369

DPU_REG_WRITE(c, ubwc_error_off, BIT(31));

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

411

DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_LR, lr_pe[0]);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

412

DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_TB, tb_pe[0]);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

413

DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_REQ_PIXELS,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

417

DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_LR, lr_pe[1]);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

418

DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_TB, tb_pe[1]);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

419

DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

423

DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_LR, lr_pe[3]);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

424

DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_TB, lr_pe[3]);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

425

DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_REQ_PIXELS,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

483

DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + i * 0x4,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

486

DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

488

DPU_REG_WRITE(&ctx->hw, SSPP_SRC2_ADDR,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

491

DPU_REG_WRITE(&ctx->hw, SSPP_SRC1_ADDR,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

493

DPU_REG_WRITE(&ctx->hw, SSPP_SRC3_ADDR,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

521

DPU_REG_WRITE(&ctx->hw, SSPP_SRC_YSTRIDE0, ystride0);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

522

DPU_REG_WRITE(&ctx->hw, SSPP_SRC_YSTRIDE1, ystride1);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

571

DPU_REG_WRITE(&ctx->hw, const_clr_off, color);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

588

DPU_REG_WRITE(&ctx->hw, ctrl_off,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h

375

DPU_REG_WRITE(c, src_size_off, src_size);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h

376

DPU_REG_WRITE(c, src_xy_off, src_xy);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h

377

DPU_REG_WRITE(c, out_size_off, dst_size);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h

378

DPU_REG_WRITE(c, out_xy_off, dst_xy);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c

185

DPU_REG_WRITE(c, SSPP_REC_SW_PIX_EXT_LR + offset, lr_pe[0]);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c

186

DPU_REG_WRITE(c, SSPP_REC_SW_PIX_EXT_TB + offset, tb_pe[0]);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c

189

DPU_REG_WRITE(c, SSPP_REC_SW_PIX_EXT_LR_ODX + offset, lr_pe[1]);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c

190

DPU_REG_WRITE(c, SSPP_REC_SW_PIX_EXT_TB_ODX + offset, tb_pe[1]);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c

227

DPU_REG_WRITE(&ctx->hw, offset + SSPP_REC_SRC0_ADDR + i * 0x4,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c

233

DPU_REG_WRITE(&ctx->hw, offset + SSPP_REC_SRC_YSTRIDE0, ystride0);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c

234

DPU_REG_WRITE(&ctx->hw, offset + SSPP_REC_SRC_YSTRIDE1, ystride1);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c

147

DPU_REG_WRITE(c, wd_load_value,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c

150

DPU_REG_WRITE(c, wd_ctl, BIT(0)); /* clear timer */

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c

154

DPU_REG_WRITE(c, wd_ctl2, reg);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c

183

DPU_REG_WRITE(c, MDP_VSYNC_SEL, reg);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c

226

DPU_REG_WRITE(c, HDMI_DP_CORE_SELECT, 0x1);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c

256

DPU_REG_WRITE(c, MDP_DP_PHY_INTF_SEL, sel);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c

57

DPU_REG_WRITE(c, SSPP_SPARE, cfg->split_flush_en ? 0x1 : 0x0);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c

58

DPU_REG_WRITE(c, SPLIT_DISPLAY_LOWER_PIPE_CTRL, lower_pipe);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c

59

DPU_REG_WRITE(c, SPLIT_DISPLAY_UPPER_PIPE_CTRL, upper_pipe);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c

60

DPU_REG_WRITE(c, SPLIT_DISPLAY_EN, cfg->en & 0x1);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

180

DPU_REG_WRITE(c,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

190

DPU_REG_WRITE(c, QSEED3_COEF_LUT_CTRL + offset, BIT(0));

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

204

DPU_REG_WRITE(c, QSEED3LITE_DIR_FILTER_WEIGHT + offset, scaler3_cfg->dir_weight);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

232

DPU_REG_WRITE(c,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

241

DPU_REG_WRITE(c, QSEED3_COEF_LUT_CTRL + offset, BIT(0));

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

279

DPU_REG_WRITE(c, QSEED3_DE_SHARPEN + offset, sharp_lvl);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

280

DPU_REG_WRITE(c, QSEED3_DE_SHARPEN_CTL + offset, sharp_ctl);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

281

DPU_REG_WRITE(c, QSEED3_DE_SHAPE_CTL + offset, shape_ctl);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

282

DPU_REG_WRITE(c, QSEED3_DE_THRESHOLD + offset, de_thr);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

283

DPU_REG_WRITE(c, QSEED3_DE_ADJUST_DATA_0 + offset, adjust_a);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

284

DPU_REG_WRITE(c, QSEED3_DE_ADJUST_DATA_1 + offset, adjust_b);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

285

DPU_REG_WRITE(c, QSEED3_DE_ADJUST_DATA_2 + offset, adjust_c);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

344

DPU_REG_WRITE(c, QSEED3_PHASE_INIT + scaler_offset, phase_init);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

346

DPU_REG_WRITE(c, QSEED3_PHASE_INIT_Y_H + scaler_offset,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

348

DPU_REG_WRITE(c, QSEED3_PHASE_INIT_Y_V + scaler_offset,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

350

DPU_REG_WRITE(c, QSEED3_PHASE_INIT_UV_H + scaler_offset,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

352

DPU_REG_WRITE(c, QSEED3_PHASE_INIT_UV_V + scaler_offset,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

356

DPU_REG_WRITE(c, QSEED3_PHASE_STEP_Y_H + scaler_offset,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

359

DPU_REG_WRITE(c, QSEED3_PHASE_STEP_Y_V + scaler_offset,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

362

DPU_REG_WRITE(c, QSEED3_PHASE_STEP_UV_H + scaler_offset,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

365

DPU_REG_WRITE(c, QSEED3_PHASE_STEP_UV_V + scaler_offset,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

368

DPU_REG_WRITE(c, QSEED3_PRELOAD + scaler_offset, preload);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

370

DPU_REG_WRITE(c, QSEED3_SRC_SIZE_Y_RGB_A + scaler_offset, src_y_rgb);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

372

DPU_REG_WRITE(c, QSEED3_SRC_SIZE_UV + scaler_offset, src_uv);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

374

DPU_REG_WRITE(c, QSEED3_DST_SIZE + scaler_offset, dst);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

388

DPU_REG_WRITE(c, QSEED3_OP_MODE + scaler_offset, op_mode);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

402

DPU_REG_WRITE(c, csc_reg_off, val);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

405

DPU_REG_WRITE(c, csc_reg_off + 0x4, val);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

408

DPU_REG_WRITE(c, csc_reg_off + 0x8, val);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

411

DPU_REG_WRITE(c, csc_reg_off + 0xc, val);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

413

DPU_REG_WRITE(c, csc_reg_off + 0x10, val);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

417

DPU_REG_WRITE(c, csc_reg_off + 0x14, val);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

419

DPU_REG_WRITE(c, csc_reg_off + 0x18, val);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

421

DPU_REG_WRITE(c, csc_reg_off + 0x1c, val);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

425

DPU_REG_WRITE(c, csc_reg_off + 0x20, val);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

427

DPU_REG_WRITE(c, csc_reg_off + 0x24, val);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

429

DPU_REG_WRITE(c, csc_reg_off + 0x28, val);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

432

DPU_REG_WRITE(c, csc_reg_off + 0x2c, data->csc_pre_bv[0]);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

433

DPU_REG_WRITE(c, csc_reg_off + 0x30, data->csc_pre_bv[1]);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

434

DPU_REG_WRITE(c, csc_reg_off + 0x34, data->csc_pre_bv[2]);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

437

DPU_REG_WRITE(c, csc_reg_off + 0x38, data->csc_post_bv[0]);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

438

DPU_REG_WRITE(c, csc_reg_off + 0x3c, data->csc_post_bv[1]);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

439

DPU_REG_WRITE(c, csc_reg_off + 0x40, data->csc_post_bv[2]);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

471

DPU_REG_WRITE(c, offset + QOS_DANGER_LUT, cfg->danger_lut);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

472

DPU_REG_WRITE(c, offset + QOS_SAFE_LUT, cfg->safe_lut);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

475

DPU_REG_WRITE(c, offset + QOS_CREQ_LUT_0, cfg->creq_lut);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

476

DPU_REG_WRITE(c, offset + QOS_CREQ_LUT_1, cfg->creq_lut >> 32);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

478

DPU_REG_WRITE(c, offset + QOS_CREQ_LUT, cfg->creq_lut);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

481

DPU_REG_WRITE(c, offset + QOS_QOS_CTRL,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

488

DPU_REG_WRITE(c, SSPP_CMN_DANGER_LUT, cfg->danger_lut);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

489

DPU_REG_WRITE(c, SSPP_CMN_SAFE_LUT, cfg->safe_lut);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

490

DPU_REG_WRITE(c, SSPP_CMN_CREQ_LUT_0, cfg->creq_lut);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

491

DPU_REG_WRITE(c, SSPP_CMN_CREQ_LUT_1, cfg->creq_lut >> 32);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

492

DPU_REG_WRITE(c, SSPP_CMN_QOS_CTRL,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

504

DPU_REG_WRITE(c, misr_ctrl_offset, MISR_CTRL_STATUS_CLEAR);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

511

DPU_REG_WRITE(c, misr_ctrl_offset, config);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

555

DPU_REG_WRITE(c, offset, cdp_cntl);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

572

DPU_REG_WRITE(c, clk_ctrl_reg->reg_off, new_val);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

105

DPU_REG_WRITE(c, reg_off, reg_val);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

143

DPU_REG_WRITE(c, VBIF_XIN_HALT_CTRL0, reg_val);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

183

DPU_REG_WRITE(c, VBIF_XINL_QOS_RP_REMAP_000 + reg_high, reg_val);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

184

DPU_REG_WRITE(c, reg_lvl + reg_high, reg_val_lvl);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

199

DPU_REG_WRITE(c, VBIF_WRITE_GATHER_EN, reg_val);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

54

DPU_REG_WRITE(c, VBIF_XIN_CLR_ERR, pnd | src);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

84

DPU_REG_WRITE(c, reg_off, reg_val);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c

115

DPU_REG_WRITE(c, WB_ALPHA_X_VALUE, 0xFF);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c

116

DPU_REG_WRITE(c, WB_DST_FORMAT, dst_format);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c

117

DPU_REG_WRITE(c, WB_DST_OP_MODE, opmode);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c

118

DPU_REG_WRITE(c, WB_DST_PACK_PATTERN, pattern);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c

119

DPU_REG_WRITE(c, WB_DST_YSTRIDE0, ystride0);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c

120

DPU_REG_WRITE(c, WB_DST_YSTRIDE1, ystride1);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c

121

DPU_REG_WRITE(c, WB_OUT_SIZE, outsize);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c

122

DPU_REG_WRITE(c, WB_DST_WRITE_CONFIG, write_config);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c

123

DPU_REG_WRITE(c, WB_DST_ADDR_SW_STATUS, dst_addr_sw);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c

135

DPU_REG_WRITE(c, WB_OUT_IMAGE_SIZE, image_size);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c

136

DPU_REG_WRITE(c, WB_OUT_XY, out_xy);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c

137

DPU_REG_WRITE(c, WB_OUT_SIZE, out_size);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c

192

DPU_REG_WRITE(c, WB_MUX, mux_cfg);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c

60

DPU_REG_WRITE(c, WB_DST0_ADDR, data->dest.plane_addr[0]);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c

61

DPU_REG_WRITE(c, WB_DST1_ADDR, data->dest.plane_addr[1]);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c

62

DPU_REG_WRITE(c, WB_DST2_ADDR, data->dest.plane_addr[2]);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c

63

DPU_REG_WRITE(c, WB_DST3_ADDR, data->dest.plane_addr[3]);