drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c

214

mux_cfg = DPU_REG_READ(c, CDM_MUX);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

103

return !!(DPU_REG_READ(&ctx->hw, CTL_START) & BIT(0));

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

425

status = DPU_REG_READ(c, CTL_SW_RESET);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

451

status = DPU_REG_READ(c, CTL_SW_RESET);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

591

intf_active = DPU_REG_READ(c, CTL_INTF_ACTIVE);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

592

wb_active = DPU_REG_READ(c, CTL_WB_ACTIVE);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

593

cwb_active = DPU_REG_READ(c, CTL_CWB_ACTIVE);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

594

dsc_active = DPU_REG_READ(c, CTL_DSC_ACTIVE);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

595

merge_3d_active = DPU_REG_READ(c, CTL_MERGE_3D_ACTIVE);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

680

merge3d_active = DPU_REG_READ(c, CTL_MERGE_3D_ACTIVE);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

699

intf_active = DPU_REG_READ(c, CTL_INTF_ACTIVE);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

703

intf_master = DPU_REG_READ(c, CTL_INTF_MASTER);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

713

cwb_active = DPU_REG_READ(c, CTL_CWB_ACTIVE);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

719

wb_active = DPU_REG_READ(c, CTL_WB_ACTIVE);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

725

dsc_active = DPU_REG_READ(c, CTL_DSC_ACTIVE);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

731

cdm_active = DPU_REG_READ(c, CTL_CDM_ACTIVE);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

91

return DPU_REG_READ(c, CTL_FLUSH);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

350

irq_status = DPU_REG_READ(&intr->hw, intr->intr_set[reg_idx].status_off);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

353

enable_mask = DPU_REG_READ(&intr->hw, intr->intr_set[reg_idx].en_off);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

560

intr_status = DPU_REG_READ(&intr->hw,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

123

intf_cfg = DPU_REG_READ(c, INTF_CONFIG);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

280

fetch_enable = DPU_REG_READ(c, INTF_CONFIG);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

299

mux_cfg = DPU_REG_READ(c, INTF_MUX);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

317

s->is_en = DPU_REG_READ(c, INTF_STATUS) & BIT(0);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

319

s->is_en = DPU_REG_READ(c, INTF_TIMING_ENGINE_EN);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

321

s->is_prog_fetch_en = !!(DPU_REG_READ(c, INTF_CONFIG) & BIT(31));

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

323

s->frame_count = DPU_REG_READ(c, INTF_FRAME_COUNT);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

324

s->line_count = DPU_REG_READ(c, INTF_LINE_COUNT);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

340

return DPU_REG_READ(c, INTF_LINE_COUNT);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

393

refresh_cfg = DPU_REG_READ(c, INTF_TEAR_AUTOREFRESH_CONFIG);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

412

u32 val = DPU_REG_READ(&intf->hw, INTF_TEAR_AUTOREFRESH_CONFIG);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

442

cfg = DPU_REG_READ(c, INTF_TEAR_SYNC_CONFIG_VSYNC);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

465

val = DPU_REG_READ(c, INTF_TEAR_VSYNC_INIT_VAL);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

468

val = DPU_REG_READ(c, INTF_TEAR_INT_COUNT_VAL);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

472

val = DPU_REG_READ(c, INTF_TEAR_LINE_COUNT);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

475

val = DPU_REG_READ(c, INTF_FRAME_COUNT);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

577

u32 intf_cfg2 = DPU_REG_READ(&intf->hw, INTF_CONFIG2);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c

193

op_mode = DPU_REG_READ(c, LM_OP_MODE);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c

216

op_mode = DPU_REG_READ(c, LM_BLEND0_OP + stage_off);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c

73

op_mode = DPU_REG_READ(c, LM_OP_MODE);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c

127

u32 val = DPU_REG_READ(&pp->hw, PP_AUTOREFRESH_CONFIG);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c

156

cfg = DPU_REG_READ(c, PP_SYNC_CONFIG_VSYNC);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c

178

val = DPU_REG_READ(c, PP_VSYNC_INIT_VAL);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c

181

val = DPU_REG_READ(c, PP_INT_COUNT_VAL);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c

185

val = DPU_REG_READ(c, PP_LINE_COUNT);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c

201

init = DPU_REG_READ(c, PP_VSYNC_INIT_VAL) & 0xFFFF;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c

202

height = DPU_REG_READ(c, PP_SYNC_CONFIG_HEIGHT) & 0xFFFF;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c

207

line = DPU_REG_READ(c, PP_INT_COUNT_VAL) & 0xFFFF;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c

280

data = DPU_REG_READ(pp_c, PP_DCE_DATA_OUT_SWAP);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

170

mode_mask = DPU_REG_READ(&ctx->hw, op_mode_off);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

191

opmode = DPU_REG_READ(&ctx->hw, sblk->scaler_blk.base + SSPP_VIG_OP_MODE);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

207

opmode = DPU_REG_READ(&ctx->hw, sblk->csc_blk.base + SSPP_VIG_CSC_10_OP_MODE);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

274

opmode = DPU_REG_READ(c, op_mode_off);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

503

ystride0 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE0);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

504

ystride1 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE1);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c

151

reg = DPU_REG_READ(c, wd_ctl2);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c

173

reg = DPU_REG_READ(c, MDP_VSYNC_SEL);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c

199

value = DPU_REG_READ(c, SAFE_STATUS);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c

87

value = DPU_REG_READ(c, DANGER_STATUS);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

524

ctrl = DPU_REG_READ(c, misr_ctrl_offset);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

532

*misr_value = DPU_REG_READ(c, misr_signature_offset);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

565

reg_val = DPU_REG_READ(c, clk_ctrl_reg->reg_off);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

102

reg_val = DPU_REG_READ(c, reg_off);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

124

reg_val = DPU_REG_READ(c, reg_off);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

136

reg_val = DPU_REG_READ(c, VBIF_XIN_HALT_CTRL0);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

152

reg_val = DPU_REG_READ(c, VBIF_XIN_HALT_CTRL1);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

172

reg_val = DPU_REG_READ(c, VBIF_XINL_QOS_RP_REMAP_000 + reg_high);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

173

reg_val_lvl = DPU_REG_READ(c, reg_lvl + reg_high);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

197

reg_val = DPU_REG_READ(c, VBIF_WRITE_GATHER_EN);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

46

pnd = DPU_REG_READ(c, VBIF_XIN_PND_ERR);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

47

src = DPU_REG_READ(c, VBIF_XIN_SRC_ERR);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

81

reg_val = DPU_REG_READ(c, reg_off);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c

182

mux_cfg = DPU_REG_READ(c, WB_MUX);