drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

423

if (cache_irq_mask & DPU_IRQ_MASK(irq_idx)) {

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

428

cache_irq_mask |= DPU_IRQ_MASK(irq_idx);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

430

DPU_REG_WRITE(&intr->hw, reg->clr_off, DPU_IRQ_MASK(irq_idx));

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

442

DPU_IRQ_MASK(irq_idx), cache_irq_mask);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

475

if ((cache_irq_mask & DPU_IRQ_MASK(irq_idx)) == 0) {

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

480

cache_irq_mask &= ~DPU_IRQ_MASK(irq_idx);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

484

DPU_REG_WRITE(&intr->hw, reg->clr_off, DPU_IRQ_MASK(irq_idx));

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

494

DPU_IRQ_MASK(irq_idx), cache_irq_mask);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

562

DPU_IRQ_MASK(irq_idx);