drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h

125

.clk_ctrl = DPU_CLK_CTRL_DMA3,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h

34

[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 12 },

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h

128

.clk_ctrl = DPU_CLK_CTRL_DMA3,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h

34

[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h

131

.clk_ctrl = DPU_CLK_CTRL_DMA3,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h

34

[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h

131

.clk_ctrl = DPU_CLK_CTRL_DMA3,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h

34

[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h

101

.clk_ctrl = DPU_CLK_CTRL_DMA3,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h

28

[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h

130

.clk_ctrl = DPU_CLK_CTRL_DMA3,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h

32

[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h

130

.clk_ctrl = DPU_CLK_CTRL_DMA3,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h

32

[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h

129

.clk_ctrl = DPU_CLK_CTRL_DMA3,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h

32

[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h

130

.clk_ctrl = DPU_CLK_CTRL_DMA3,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h

32

[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h

129

.clk_ctrl = DPU_CLK_CTRL_DMA3,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h

31

[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },