drivers/gpu/drm/i915/display/intel_display.c

8400

intel_de_write(display, DPLL(display, pipe),

drivers/gpu/drm/i915/display/intel_display.c

8402

intel_de_write(display, DPLL(display, pipe), dpll);

drivers/gpu/drm/i915/display/intel_display.c

8405

intel_de_posting_read(display, DPLL(display, pipe));

drivers/gpu/drm/i915/display/intel_display.c

8413

intel_de_write(display, DPLL(display, pipe), dpll);

drivers/gpu/drm/i915/display/intel_display.c

8417

intel_de_write(display, DPLL(display, pipe), dpll);

drivers/gpu/drm/i915/display/intel_display.c

8418

intel_de_posting_read(display, DPLL(display, pipe));

drivers/gpu/drm/i915/display/intel_display.c

8451

intel_de_write(display, DPLL(display, pipe), DPLL_VGA_MODE_DIS);

drivers/gpu/drm/i915/display/intel_display.c

8452

intel_de_posting_read(display, DPLL(display, pipe));

drivers/gpu/drm/i915/display/intel_display_power.c

1801

u32 status = intel_de_read(display, DPLL(display, PIPE_A));

drivers/gpu/drm/i915/display/intel_display_power_well.c

1301

u32 val = intel_de_read(display, DPLL(display, pipe));

drivers/gpu/drm/i915/display/intel_display_power_well.c

1307

intel_de_write(display, DPLL(display, pipe), val);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1457

(intel_de_read(display, DPLL(display, PIPE_B)) & DPLL_VCO_ENABLE) == 0)

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1184

dpll_reg = DPLL(display, 0);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1188

dpll_reg = DPLL(display, 0);

drivers/gpu/drm/i915/display/intel_dpll.c

1832

intel_de_write(display, DPLL(display, pipe),

drivers/gpu/drm/i915/display/intel_dpll.c

1834

intel_de_write(display, DPLL(display, pipe), hw_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll.c

1837

intel_de_posting_read(display, DPLL(display, pipe));

drivers/gpu/drm/i915/display/intel_dpll.c

1849

intel_de_write(display, DPLL(display, pipe), hw_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll.c

1854

intel_de_write(display, DPLL(display, pipe), hw_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll.c

1855

intel_de_posting_read(display, DPLL(display, pipe));

drivers/gpu/drm/i915/display/intel_dpll.c

1977

intel_de_write(display, DPLL(display, pipe), hw_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll.c

1978

intel_de_posting_read(display, DPLL(display, pipe));

drivers/gpu/drm/i915/display/intel_dpll.c

1981

if (intel_de_wait_for_set_ms(display, DPLL(display, pipe), DPLL_LOCK_VLV, 1))

drivers/gpu/drm/i915/display/intel_dpll.c

1998

intel_de_write(display, DPLL(display, pipe),

drivers/gpu/drm/i915/display/intel_dpll.c

2124

intel_de_write(display, DPLL(display, pipe), hw_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll.c

2127

if (intel_de_wait_for_set_ms(display, DPLL(display, pipe), DPLL_LOCK_VLV, 1))

drivers/gpu/drm/i915/display/intel_dpll.c

2144

intel_de_write(display, DPLL(display, pipe),

drivers/gpu/drm/i915/display/intel_dpll.c

2170

(intel_de_read(display, DPLL(display, PIPE_B)) &

drivers/gpu/drm/i915/display/intel_dpll.c

2229

intel_de_write(display, DPLL(display, pipe), val);

drivers/gpu/drm/i915/display/intel_dpll.c

2230

intel_de_posting_read(display, DPLL(display, pipe));

drivers/gpu/drm/i915/display/intel_dpll.c

2247

intel_de_write(display, DPLL(display, pipe), val);

drivers/gpu/drm/i915/display/intel_dpll.c

2248

intel_de_posting_read(display, DPLL(display, pipe));

drivers/gpu/drm/i915/display/intel_dpll.c

2273

intel_de_write(display, DPLL(display, pipe), DPLL_VGA_MODE_DIS);

drivers/gpu/drm/i915/display/intel_dpll.c

2274

intel_de_posting_read(display, DPLL(display, pipe));

drivers/gpu/drm/i915/display/intel_dpll.c

2300

cur_state = intel_de_read(display, DPLL(display, pipe)) & DPLL_VCO_ENABLE;

drivers/gpu/drm/i915/display/intel_dpll.c

410

hw_state->dpll = intel_de_read(display, DPLL(display, crtc->pipe));

drivers/gpu/drm/i915/display/intel_dvo.c

446

dpll[pipe] = intel_de_rmw(display, DPLL(display, pipe), 0,

drivers/gpu/drm/i915/display/intel_dvo.c

453

intel_de_write(display, DPLL(display, pipe), dpll[pipe]);

drivers/gpu/drm/i915/display/intel_pps.c

129

pll_enabled = intel_de_read(display, DPLL(display, pipe)) & DPLL_VCO_ENABLE;