DPRAM_BASE
out_be16(&i2c_ram->tbase, (u8 __iomem *)cpm->tbase - DPRAM_BASE);
out_be16(&i2c_ram->rbase, (u8 __iomem *)cpm->rbase - DPRAM_BASE);
(u8 __iomem *)cpm->tbase - DPRAM_BASE,
(u8 __iomem *)cpm->rbase - DPRAM_BASE);
start_debi_dma(av7110, DEBI_WRITE, DPRAM_BASE + txbuf, len);
start_debi_dma(av7110, DEBI_WRITE, DPRAM_BASE + txbuf, len);
start_debi_dma(av7110, DEBI_WRITE, DPRAM_BASE + txbuf, len);
start_debi_dma(av7110, DEBI_READ, DPRAM_BASE + rxbuf, len);
iwdebi(av7110, DEBISWAP, DPRAM_BASE, 0x76543210, 4);
iwdebi(av7110, DEBISWAP, DPRAM_BASE, 0x76543210, 4);
ret = irdebi(av7110, DEBINOSWAP, DPRAM_BASE, 0, 4);
iwdebi(av7110, DEBISWAP, DPRAM_BASE + i, 0x00, 4);
mwdebi(av7110, DEBISWAB, DPRAM_BASE, fw->data, fw->size);
mwdebi(av7110, DEBISWAB, DPRAM_BASE, av7110->bin_dpram, av7110->size_dpram);
#define AV7110_BOOT_STATE (DPRAM_BASE + 0x3F8)
#define AV7110_BOOT_SIZE (DPRAM_BASE + 0x3FA)
#define AV7110_BOOT_BASE (DPRAM_BASE + 0x3FC)
#define AV7110_BOOT_BLOCK (DPRAM_BASE + 0x400)
#define IRQ_STATE (DPRAM_BASE + 0x0F4)
#define IRQ_STATE_EXT (DPRAM_BASE + 0x0F6)
#define MSGSTATE (DPRAM_BASE + 0x0F8)
#define COMMAND (DPRAM_BASE + 0x0FC)
#define COM_BUFF (DPRAM_BASE + 0x100)
#define BUFF1_BASE (DPRAM_BASE + 0x120)
#define DATA_BUFF0_BASE (DPRAM_BASE + 0x200)
#define Reserved (DPRAM_BASE + 0x1E00)
#define STATUS_BASE (DPRAM_BASE + 0x1FC0)
#define RX_TYPE (DPRAM_BASE + 0x1FE8)
#define RX_LEN (DPRAM_BASE + 0x1FEA)
#define TX_TYPE (DPRAM_BASE + 0x1FEC)
#define TX_LEN (DPRAM_BASE + 0x1FEE)
#define RX_BUFF (DPRAM_BASE + 0x1FF4)
#define TX_BUFF (DPRAM_BASE + 0x1FF6)
#define HANDSHAKE_REG (DPRAM_BASE + 0x1FF8)
#define COM_IF_LOCK (DPRAM_BASE + 0x1FFA)
#define IRQ_RX (DPRAM_BASE + 0x1FFC)
#define IRQ_TX (DPRAM_BASE + 0x1FFE)
(u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE);
(u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE);
(u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE);
(u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE);