drivers/gpu/drm/i915/display/intel_display.c

8375

intel_de_write(display, DPLL(display, pipe),

drivers/gpu/drm/i915/display/intel_display.c

8377

intel_de_write(display, DPLL(display, pipe), dpll);

drivers/gpu/drm/i915/display/intel_display.c

8380

intel_de_posting_read(display, DPLL(display, pipe));

drivers/gpu/drm/i915/display/intel_display.c

8388

intel_de_write(display, DPLL(display, pipe), dpll);

drivers/gpu/drm/i915/display/intel_display.c

8392

intel_de_write(display, DPLL(display, pipe), dpll);

drivers/gpu/drm/i915/display/intel_display.c

8393

intel_de_posting_read(display, DPLL(display, pipe));

drivers/gpu/drm/i915/display/intel_display.c

8426

intel_de_write(display, DPLL(display, pipe), DPLL_VGA_MODE_DIS);

drivers/gpu/drm/i915/display/intel_display.c

8427

intel_de_posting_read(display, DPLL(display, pipe));

drivers/gpu/drm/i915/display/intel_display_power.c

1805

u32 status = intel_de_read(display, DPLL(display, PIPE_A));

drivers/gpu/drm/i915/display/intel_display_power_well.c

1256

u32 val = intel_de_read(display, DPLL(display, pipe));

drivers/gpu/drm/i915/display/intel_display_power_well.c

1262

intel_de_write(display, DPLL(display, pipe), val);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1412

(intel_de_read(display, DPLL(display, PIPE_B)) & DPLL_VCO_ENABLE) == 0)

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1184

dpll_reg = DPLL(display, 0);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1188

dpll_reg = DPLL(display, 0);

drivers/gpu/drm/i915/display/intel_dpll.c

1853

intel_de_write(display, DPLL(display, pipe),

drivers/gpu/drm/i915/display/intel_dpll.c

1855

intel_de_write(display, DPLL(display, pipe), hw_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll.c

1858

intel_de_posting_read(display, DPLL(display, pipe));

drivers/gpu/drm/i915/display/intel_dpll.c

1870

intel_de_write(display, DPLL(display, pipe), hw_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll.c

1875

intel_de_write(display, DPLL(display, pipe), hw_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll.c

1876

intel_de_posting_read(display, DPLL(display, pipe));

drivers/gpu/drm/i915/display/intel_dpll.c

1998

intel_de_write(display, DPLL(display, pipe), hw_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll.c

1999

intel_de_posting_read(display, DPLL(display, pipe));

drivers/gpu/drm/i915/display/intel_dpll.c

2002

if (intel_de_wait_for_set_ms(display, DPLL(display, pipe), DPLL_LOCK_VLV, 1))

drivers/gpu/drm/i915/display/intel_dpll.c

2019

intel_de_write(display, DPLL(display, pipe),

drivers/gpu/drm/i915/display/intel_dpll.c

2145

intel_de_write(display, DPLL(display, pipe), hw_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll.c

2148

if (intel_de_wait_for_set_ms(display, DPLL(display, pipe), DPLL_LOCK_VLV, 1))

drivers/gpu/drm/i915/display/intel_dpll.c

2165

intel_de_write(display, DPLL(display, pipe),

drivers/gpu/drm/i915/display/intel_dpll.c

2191

(intel_de_read(display, DPLL(display, PIPE_B)) &

drivers/gpu/drm/i915/display/intel_dpll.c

2250

intel_de_write(display, DPLL(display, pipe), val);

drivers/gpu/drm/i915/display/intel_dpll.c

2251

intel_de_posting_read(display, DPLL(display, pipe));

drivers/gpu/drm/i915/display/intel_dpll.c

2268

intel_de_write(display, DPLL(display, pipe), val);

drivers/gpu/drm/i915/display/intel_dpll.c

2269

intel_de_posting_read(display, DPLL(display, pipe));

drivers/gpu/drm/i915/display/intel_dpll.c

2294

intel_de_write(display, DPLL(display, pipe), DPLL_VGA_MODE_DIS);

drivers/gpu/drm/i915/display/intel_dpll.c

2295

intel_de_posting_read(display, DPLL(display, pipe));

drivers/gpu/drm/i915/display/intel_dpll.c

2321

cur_state = intel_de_read(display, DPLL(display, pipe)) & DPLL_VCO_ENABLE;

drivers/gpu/drm/i915/display/intel_dpll.c

410

hw_state->dpll = intel_de_read(display, DPLL(display, crtc->pipe));

drivers/gpu/drm/i915/display/intel_dvo.c

461

dpll[pipe] = intel_de_rmw(display, DPLL(display, pipe), 0,

drivers/gpu/drm/i915/display/intel_dvo.c

468

intel_de_write(display, DPLL(display, pipe), dpll[pipe]);

drivers/gpu/drm/i915/display/intel_pps.c

130

pll_enabled = intel_de_read(display, DPLL(display, pipe)) & DPLL_VCO_ENABLE;