drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

184

REG_UPDATE(DPG_PIPE_ARBITRATION_CONTROL3,

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h

133

uint32_t DPG_PIPE_ARBITRATION_CONTROL3;

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h

251

SFB(blk, DPG_PIPE_ARBITRATION_CONTROL3, URGENCY_WATERMARK_MASK, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h

79

SRI(DPG_PIPE_ARBITRATION_CONTROL3, DMIF_PG, id),\

drivers/gpu/drm/radeon/si.c

2411

arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);

drivers/gpu/drm/radeon/si.c

2415

WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);

drivers/gpu/drm/radeon/si.c

2420

tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);

drivers/gpu/drm/radeon/si.c

2423

WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);

drivers/gpu/drm/radeon/si.c

2428

WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3);