DMA_CONTROL
writel(DMA_CONTROL_ENABLE, host->addr + DMA_CONTROL);
writel(0, host->addr + DMA_CONTROL);
val = emac_rd(priv, DMA_CONTROL);
emac_wr(priv, DMA_CONTROL, val);
val = emac_rd(priv, DMA_CONTROL);
emac_wr(priv, DMA_CONTROL, val);
emac_wr(priv, DMA_CONTROL, 0x0);
emac_wr(priv, DMA_CONTROL, 0x0);
u32 csr6 = readl(ioaddr + DMA_CONTROL);
writel(csr6, ioaddr + DMA_CONTROL);
#define DMA_CHAN_CONTROL(chan) dma_chan_base_addr(DMA_CONTROL, chan)
u32 csr6 = readl(ioaddr + DMA_CONTROL);
writel((csr6 | DMA_CONTROL_FTF), ioaddr + DMA_CONTROL);
do {} while ((readl(ioaddr + DMA_CONTROL) & DMA_CONTROL_FTF));
old = inb(ICEMT1724(ice, DMA_CONTROL));
outb(old, ICEMT1724(ice, DMA_CONTROL));
if ((inb(ICEMT1724(ice, DMA_CONTROL)) & DMA_STARTS) ||
if (!(inl(ICEMT1724(ice, DMA_CONTROL)) & VT1724_PDMA0_START))
if (!(inl(ICEMT1724(ice, DMA_CONTROL)) & reg->start))