DMA_ATTR_SKIP_CPU_SYNC
if (!dev_dma_coherent(dev) && !(attrs & DMA_ATTR_SKIP_CPU_SYNC))
if (!dev_dma_coherent(dev) && !(attrs & DMA_ATTR_SKIP_CPU_SYNC))
!(attrs & (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_MMIO)))
!(attrs & (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_MMIO))) {
if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
if (strbuf->strbuf_enabled && !(attrs & DMA_ATTR_SKIP_CPU_SYNC))
if (strbuf->strbuf_enabled && !(attrs & DMA_ATTR_SKIP_CPU_SYNC))
direction, DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC);
ret = dma_map_sgtable(attachment->dev, sgt, direction, DMA_ATTR_SKIP_CPU_SYNC);
dma_unmap_sgtable(attachment->dev, sgt, direction, DMA_ATTR_SKIP_CPU_SYNC);
ctx->dir, DMA_ATTR_SKIP_CPU_SYNC);
ctx->dir, DMA_ATTR_SKIP_CPU_SYNC);
ctx->dir, DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC);
DMA_BIDIRECTIONAL, DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC);
ctx->dir, DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC);
ctx->dir, DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC);
ret = dma_map_sgtable(dev, sg, direction, DMA_ATTR_SKIP_CPU_SYNC);
dma_unmap_sgtable(dev, sg, direction, DMA_ATTR_SKIP_CPU_SYNC);
DMA_TO_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC);
mem->bo->tbo.sg->sgl->length, dir, DMA_ATTR_SKIP_CPU_SYNC);
dir, DMA_ATTR_SKIP_CPU_SYNC);
ttm->sg->sgl->length, dir, DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC))
DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC);
dma = dma_map_resource(dev, phys, cur.size, dir, DMA_ATTR_SKIP_CPU_SYNC);
dir, DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC);
dma_unmap_sgtable(attach->dev, sgt, dir, DMA_ATTR_SKIP_CPU_SYNC);
ret = dma_map_sgtable(attach->dev, sgt, dir, DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC |
DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC))
DMA_ATTR_SKIP_CPU_SYNC);
addr->dir, DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC);
if (!coherent && !(attrs & (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_MMIO))) {
if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC) && !dev_is_dma_coherent(dev)) {
iommu_dma_unmap_sg_swiotlb(dev, sg, i, dir, attrs | DMA_ATTR_SKIP_CPU_SYNC);
if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
if (!coherent && !(attrs & (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_MMIO)))
!(attrs & (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_MMIO));
!(attrs & (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_MMIO)))
!(attrs & (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_MMIO))))
DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC)) {
DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC)) {
dma_unmap_sgtable(buf->dev, sgt, buf->dma_dir, DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC))
DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC))
dma_unmap_sgtable(buf->dev, sgt, buf->dma_dir, DMA_ATTR_SKIP_CPU_SYNC);
if ((attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0)
DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC);
ena_unmap_rx_buff_attrs(rx_ring, rx_info, DMA_ATTR_SKIP_CPU_SYNC);
ena_unmap_rx_buff_attrs(rx_ring, rx_info, DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC);
DMA_TO_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC);
DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC);
DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC);
xsk_pool_dma_unmap(pool, DMA_ATTR_SKIP_CPU_SYNC);
xsk_pool_dma_unmap(pool, DMA_ATTR_SKIP_CPU_SYNC);
DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING);
DMA_ATTR_SKIP_CPU_SYNC |
DMA_ATTR_SKIP_CPU_SYNC |
(DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
(DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
(DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
(DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
(DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
(DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
(DMA_ATTR_WEAK_ORDERING | DMA_ATTR_SKIP_CPU_SYNC)
DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC);
DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
offset, size, dir, DMA_ATTR_SKIP_CPU_SYNC);
dir, DMA_ATTR_SKIP_CPU_SYNC);
err = xsk_pool_dma_map(pool, pf->dev, DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING);
xsk_pool_dma_unmap(pool, DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING);
DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC);
return xsk_pool_dma_map(pool, dev, DMA_ATTR_SKIP_CPU_SYNC);
return xsk_pool_dma_unmap(pool, DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC);
dp->rx_dma_dir, DMA_ATTR_SKIP_CPU_SYNC);
dp->rx_dma_dir, DMA_ATTR_SKIP_CPU_SYNC);
#define STMMAC_RX_DMA_ATTR (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
#define PRUETH_RX_DMA_ATTR (DMA_ATTR_SKIP_CPU_SYNC |\
DMA_TO_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
DMA_TO_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC);
unsigned long attrs = DMA_ATTR_SKIP_CPU_SYNC;
unsigned long attrs = DMA_ATTR_SKIP_CPU_SYNC;
if ((attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0)
DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC);
if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC) &&
if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC) &&
DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC)) {
xen_grant_dma_unmap_sg(dev, sg, i, dir, attrs | DMA_ATTR_SKIP_CPU_SYNC);
attrs | DMA_ATTR_SKIP_CPU_SYNC,
if (!dev_is_dma_coherent(dev) && !(attrs & DMA_ATTR_SKIP_CPU_SYNC)) {
if (!dev_is_dma_coherent(hwdev) && !(attrs & DMA_ATTR_SKIP_CPU_SYNC)) {
xen_swiotlb_unmap_sg(dev, sgl, i, dir, attrs | DMA_ATTR_SKIP_CPU_SYNC);
{ DMA_ATTR_SKIP_CPU_SYNC, "SKIP_CPU_SYNC" }, \
#define IO_DMA_ATTR (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
} else if (rc == -EEXIST && !(attrs & DMA_ATTR_SKIP_CPU_SYNC) &&
dma_direct_unmap_sg(dev, sgl, i, dir, attrs | DMA_ATTR_SKIP_CPU_SYNC);
!(attrs & (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_MMIO))) {
if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
attrs | DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC);
DMA_ATTR_SKIP_CPU_SYNC);
if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC) &&
attrs | DMA_ATTR_SKIP_CPU_SYNC,
if (!dev_is_dma_coherent(dev) && !(attrs & DMA_ATTR_SKIP_CPU_SYNC)) {
DMA_ATTR_SKIP_CPU_SYNC |
DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING);
DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING);