drivers/gpu/drm/radeon/ni_dma.c

106

reg = DMA_RB_WPTR + DMA0_REGISTER_OFFSET;

drivers/gpu/drm/radeon/ni_dma.c

108

reg = DMA_RB_WPTR + DMA1_REGISTER_OFFSET;

drivers/gpu/drm/radeon/ni_dma.c

218

WREG32(DMA_RB_WPTR + reg_offset, 0);

drivers/gpu/drm/radeon/ni_dma.c

243

WREG32(DMA_RB_WPTR + reg_offset, ring->wptr << 2);

drivers/gpu/drm/radeon/ni_dma.c

85

reg = DMA_RB_WPTR + DMA0_REGISTER_OFFSET;

drivers/gpu/drm/radeon/ni_dma.c

87

reg = DMA_RB_WPTR + DMA1_REGISTER_OFFSET;

drivers/gpu/drm/radeon/r600_dma.c

139

WREG32(DMA_RB_WPTR, 0);

drivers/gpu/drm/radeon/r600_dma.c

167

WREG32(DMA_RB_WPTR, ring->wptr << 2);

drivers/gpu/drm/radeon/r600_dma.c

74

return (RREG32(DMA_RB_WPTR) & 0x3fffc) >> 2;

drivers/gpu/drm/radeon/r600_dma.c

88

WREG32(DMA_RB_WPTR, (ring->wptr << 2) & 0x3fffc);