drivers/dma-buf/sw_sync.c

82

#define SW_SYNC_HAS_DEADLINE_BIT DMA_FENCE_FLAG_USER_BITS

drivers/gpu/drm/i915/i915_request.h

84

I915_FENCE_FLAG_ACTIVE = DMA_FENCE_FLAG_USER_BITS,

drivers/gpu/drm/i915/i915_sw_fence_work.h

36

DMA_FENCE_WORK_IMM = DMA_FENCE_FLAG_USER_BITS,

drivers/gpu/drm/nouveau/nouveau_fence.c

527

set_bit(DMA_FENCE_FLAG_USER_BITS, &fence->base.flags);

drivers/gpu/drm/nouveau/nouveau_fence.c

56

if (test_bit(DMA_FENCE_FLAG_USER_BITS, &fence->base.flags)) {

drivers/gpu/drm/xe/xe_tlb_inval.c

30

#define FENCE_STACK_BIT DMA_FENCE_FLAG_USER_BITS

include/drm/gpu_scheduler.h

42

#define DRM_SCHED_FENCE_DONT_PIPELINE DMA_FENCE_FLAG_USER_BITS

include/drm/gpu_scheduler.h

51

#define DRM_SCHED_FENCE_FLAG_HAS_DEADLINE_BIT (DMA_FENCE_FLAG_USER_BITS + 1)