DMA_CH_TCR
XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, OSP,
XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, TSE, 1);
XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 1);
XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 0);
XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 1);
XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 0);
XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR,
regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_TCR));
writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_TCR));
regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_TCR));
writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_TCR));
regval = readl(XLGMAC_DMA_REG(pdata->channel_head, DMA_CH_TCR));
regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_TCR));
writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_TCR));
regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_TCR));
writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_TCR));
regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_TCR));
writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_TCR));