DMA_CH_SR
XGMAC_DMA_IOWRITE(channel, DMA_CH_SR,
XGMAC_DMA_IOREAD(channel, DMA_CH_SR));
dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
ti = !!XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI);
ri = !!XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI);
rbu = !!XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RBU);
fbe = !!XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, FBE);
XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, TI, 0);
XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, RI, 0);
XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr);
XGMAC_SET_BITS(dma_status, DMA_CH_SR, TI, 1);
XGMAC_SET_BITS(dma_status, DMA_CH_SR, RI, 1);
XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_status);
dma_ch_isr = readl(XLGMAC_DMA_REG(channel, DMA_CH_SR));
writel(dma_ch_isr, XLGMAC_DMA_REG(channel, DMA_CH_SR));
dma_ch_isr = readl(XLGMAC_DMA_REG(channel, DMA_CH_SR));
writel(dma_ch_isr, XLGMAC_DMA_REG(channel, DMA_CH_SR));