A0
.set USER_DA,LV+0 | save space for D0-D1,A0-A1
.set USER_A0,LV+8 | saved user A0
hdmi_info.bits.A0 = ACTIVE_FORMAT_VALID;
uint8_t A0:1;
int A0[3];
[0x0] = { COMMON_STEP(A0) },
[0x0] = { COMMON_STEP(A0) },
[0x0] = { COMMON_STEP(A0) },
[0x0] = { COMMON_STEP(A0) },
[0x0] = { COMMON_STEP(A0) },
[0] = { COMMON_STEP(A0) },
[0] = { COMMON_STEP(A0) },
[0] = { COMMON_STEP(A0) },
[0] = { COMMON_STEP(A0) },
[0] = { COMMON_STEP(A0) },
[0x0] = { COMMON_STEP(A0) },
[0x1] = { COMMON_STEP(A0) },
func(A0) \
PLATFORM_CASE(DG1, A0),
PLATFORM_CASE(ALDERLAKE_S, A0),
PLATFORM_CASE(ALDERLAKE_P, A0),
GMDID_CASE(METEORLAKE, 1270, A0, 1300, A0),
GMDID_CASE(METEORLAKE, 1271, A0, 1300, A0),
GMDID_CASE(METEORLAKE, 1274, A0, 1300, A0),
GMDID_CASE(LUNARLAKE, 2004, A0, 2000, A0),
GMDID_CASE(LUNARLAKE, 2004, B0, 2000, A0),
GMDID_CASE(BATTLEMAGE, 2001, A0, 1301, A1),
GMDID_CASE(PANTHERLAKE, 3000, A0, 3000, A0),
XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
[0] = { COMMON_STEP(A0) },
[0] = { COMMON_STEP(A0) },
[0x0] = { COMMON_STEP(A0) },
[0x1] = { COMMON_STEP(A0) },
[0x0] = { COMMON_STEP(A0) },
[0x0] = { COMMON_STEP(A0) },
[0x0] = { COMMON_STEP(A0) },
[0x0] = { COMMON_STEP(A0) },
[0x0] = { COMMON_STEP(A0) },
func(A0) \
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271), GRAPHICS_STEP(A0, B0)),
XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0)),
XE_RTP_RULES(MEDIA_VERSION(3000), MEDIA_STEP(A0, B0),
XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0),
XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0),
XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0),
XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0),
PINMUX_IPSR_GPSR(IP4_7_4, A0),
PINMUX_IPSR_GPSR(IP0_14_12, A0),
PINMUX_IPSR_GPSR(IP0_7_6, A0),
PINMUX_IPSR_GPSR(IP1_27_26, A0),
PINMUX_IPSR_GPSR(IP0_18_16, A0),
PINMUX_SINGLE(A0),
PINMUX_IPSR_GPSR(IP1_23_22, A0),
#define GPSR1_0 F_(A0, IP1_31_28)
#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
PINMUX_IPSR_GPSR(IP1_31_28, A0),
#define GPSR1_0 F_(A0, IP1_31_28)
#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
PINMUX_IPSR_GPSR(IP1_31_28, A0),
#define GPSR1_0 F_(A0, IP1_31_28)
#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
PINMUX_IPSR_GPSR(IP1_31_28, A0),
#define IP0_3_0 FM(DU_DR2) FM(HSCK0) F_(0, 0) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
PINMUX_IPSR_GPSR(IP0_3_0, A0),
#define IP0_3_0 FM(DU_DR2) FM(SCK4) FM(GETHER_RMII_CRS_DV) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
PINMUX_IPSR_GPSR(IP0_3_0, A0),
#define GPSR1_0 F_(A0, IP2_31_28)
#define IP2_31_28 FM(A0) FM(IRQ0) FM(PWM2_A) FM(MSIOF3_SS1_B) FM(VI5_CLK_A) FM(DU_CDE) FM(HRX3_D) FM(IERX) FM(QSTB_QHE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
PINMUX_IPSR_GPSR(IP2_31_28, A0),
#define IP0SR1_3_0 FM(SCIF_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
PINMUX_IPSR_GPSR(IP0SR1_3_0, A0),
GPIO_FN(A0),
GPIO_FN(A0),
GPIO_FN(A0),
GPIO_FN(A0),
GPIO_FN(A0), GPIO_FN(ST0_CLKIN), GPIO_FN(LCD_DATA0_A),
PINMUX_IPSR_GPSR(IP0_1_0, A0),
GPIO_FN(A0),