drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

1720

WREG32(mmDMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);

drivers/gpu/drm/amd/amdgpu/si.c

1127

{mmDMA_STATUS_REG + DMA1_REGISTER_OFFSET},

drivers/gpu/drm/amd/amdgpu/si_dma.c

35

DMA1_REGISTER_OFFSET

drivers/gpu/drm/amd/amdgpu/si_dma.c

618

sdma_cntl = RREG32(mmDMA_CNTL + DMA1_REGISTER_OFFSET);

drivers/gpu/drm/amd/amdgpu/si_dma.c

620

WREG32(mmDMA_CNTL + DMA1_REGISTER_OFFSET, sdma_cntl);

drivers/gpu/drm/amd/amdgpu/si_dma.c

623

sdma_cntl = RREG32(mmDMA_CNTL + DMA1_REGISTER_OFFSET);

drivers/gpu/drm/amd/amdgpu/si_dma.c

625

WREG32(mmDMA_CNTL + DMA1_REGISTER_OFFSET, sdma_cntl);

drivers/gpu/drm/amd/amdgpu/si_dma.c

663

offset = DMA1_REGISTER_OFFSET;

drivers/gpu/drm/amd/amdgpu/si_dma.c

675

offset = DMA1_REGISTER_OFFSET;

drivers/gpu/drm/radeon/ni.c

1107

WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);

drivers/gpu/drm/radeon/ni.c

1748

tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);

drivers/gpu/drm/radeon/ni.c

1831

tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);

drivers/gpu/drm/radeon/ni.c

1833

WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);

drivers/gpu/drm/radeon/ni.c

845

case (DMA_STATUS_REG + DMA1_REGISTER_OFFSET):

drivers/gpu/drm/radeon/ni_dma.c

108

reg = DMA_RB_WPTR + DMA1_REGISTER_OFFSET;

drivers/gpu/drm/radeon/ni_dma.c

170

rb_cntl = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);

drivers/gpu/drm/radeon/ni_dma.c

172

WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, rb_cntl);

drivers/gpu/drm/radeon/ni_dma.c

201

reg_offset = DMA1_REGISTER_OFFSET;

drivers/gpu/drm/radeon/ni_dma.c

63

reg = DMA_RB_RPTR + DMA1_REGISTER_OFFSET;

drivers/gpu/drm/radeon/ni_dma.c

87

reg = DMA_RB_WPTR + DMA1_REGISTER_OFFSET;

drivers/gpu/drm/radeon/si.c

1298

case (DMA_STATUS_REG + DMA1_REGISTER_OFFSET):

drivers/gpu/drm/radeon/si.c

3259

WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);

drivers/gpu/drm/radeon/si.c

3787

tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);

drivers/gpu/drm/radeon/si.c

3870

tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);

drivers/gpu/drm/radeon/si.c

3872

WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);

drivers/gpu/drm/radeon/si.c

4035

tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);

drivers/gpu/drm/radeon/si.c

4037

WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);

drivers/gpu/drm/radeon/si.c

5521

offset = DMA1_REGISTER_OFFSET;

drivers/gpu/drm/radeon/si.c

5533

offset = DMA1_REGISTER_OFFSET;

drivers/gpu/drm/radeon/si.c

5940

tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;

drivers/gpu/drm/radeon/si.c

5941

WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp);

drivers/gpu/drm/radeon/si.c

6055

dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;

drivers/gpu/drm/radeon/si.c

6088

WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, dma_cntl1);