drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

1719

WREG32(mmDMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);

drivers/gpu/drm/amd/amdgpu/si.c

1126

{mmDMA_STATUS_REG + DMA0_REGISTER_OFFSET},

drivers/gpu/drm/amd/amdgpu/si_dma.c

34

DMA0_REGISTER_OFFSET,

drivers/gpu/drm/amd/amdgpu/si_dma.c

602

sdma_cntl = RREG32(mmDMA_CNTL + DMA0_REGISTER_OFFSET);

drivers/gpu/drm/amd/amdgpu/si_dma.c

604

WREG32(mmDMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl);

drivers/gpu/drm/amd/amdgpu/si_dma.c

607

sdma_cntl = RREG32(mmDMA_CNTL + DMA0_REGISTER_OFFSET);

drivers/gpu/drm/amd/amdgpu/si_dma.c

609

WREG32(mmDMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl);

drivers/gpu/drm/amd/amdgpu/si_dma.c

661

offset = DMA0_REGISTER_OFFSET;

drivers/gpu/drm/amd/amdgpu/si_dma.c

673

offset = DMA0_REGISTER_OFFSET;

drivers/gpu/drm/radeon/ni.c

1106

WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);

drivers/gpu/drm/radeon/ni.c

1743

tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);

drivers/gpu/drm/radeon/ni.c

1824

tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);

drivers/gpu/drm/radeon/ni.c

1826

WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);

drivers/gpu/drm/radeon/ni.c

844

case (DMA_STATUS_REG + DMA0_REGISTER_OFFSET):

drivers/gpu/drm/radeon/ni_dma.c

106

reg = DMA_RB_WPTR + DMA0_REGISTER_OFFSET;

drivers/gpu/drm/radeon/ni_dma.c

165

rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);

drivers/gpu/drm/radeon/ni_dma.c

167

WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, rb_cntl);

drivers/gpu/drm/radeon/ni_dma.c

197

reg_offset = DMA0_REGISTER_OFFSET;

drivers/gpu/drm/radeon/ni_dma.c

61

reg = DMA_RB_RPTR + DMA0_REGISTER_OFFSET;

drivers/gpu/drm/radeon/ni_dma.c

85

reg = DMA_RB_WPTR + DMA0_REGISTER_OFFSET;

drivers/gpu/drm/radeon/si.c

1297

case (DMA_STATUS_REG + DMA0_REGISTER_OFFSET):

drivers/gpu/drm/radeon/si.c

3258

WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);

drivers/gpu/drm/radeon/si.c

3782

tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);

drivers/gpu/drm/radeon/si.c

3864

tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);

drivers/gpu/drm/radeon/si.c

3866

WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);

drivers/gpu/drm/radeon/si.c

4031

tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);

drivers/gpu/drm/radeon/si.c

4033

WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);

drivers/gpu/drm/radeon/si.c

5519

offset = DMA0_REGISTER_OFFSET;

drivers/gpu/drm/radeon/si.c

5531

offset = DMA0_REGISTER_OFFSET;

drivers/gpu/drm/radeon/si.c

5938

tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;

drivers/gpu/drm/radeon/si.c

5939

WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp);

drivers/gpu/drm/radeon/si.c

6054

dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;

drivers/gpu/drm/radeon/si.c

6087

WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, dma_cntl);