arch/sh/kernel/cpu/sh4a/clock-sh7343.c

115

[DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

199

CLKDEV_CON_ID("siua_clk", &div4_clks[DIV4_SIUA]),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

118

[DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

197

CLKDEV_CON_ID("siua_clk", &div4_clks[DIV4_SIUA]),

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

131

[DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

184

CLKDEV_CON_ID("siua_clk", &div4_reparent_clks[DIV4_SIUA]),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

132

[DIV4_SIUA] = DIV4(SCLKACR, 0, 0x0dbf, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

209

CLKDEV_CON_ID("siua_clk", &div4_reparent_clks[DIV4_SIUA]),