DL_GAIN_N_40DB
lo_volume_ramp(priv, DL_GAIN_N_40DB, lgain,
DL_GAIN_N_40DB, rgain);
lo_volume_ramp(priv, lgain, DL_GAIN_N_40DB,
rgain, DL_GAIN_N_40DB);
DL_GAIN_N_40DB);
hs_volume_ramp(priv, DL_GAIN_N_40DB, gain);
hs_volume_ramp(priv, gain, DL_GAIN_N_40DB);
return (reg_idx >= DL_GAIN_8DB && reg_idx <= DL_GAIN_N_12DB) || reg_idx == DL_GAIN_N_40DB;
hp_volume_ramp(priv, DL_GAIN_N_40DB, lgain,
DL_GAIN_N_40DB, rgain);
hp_volume_ramp(priv, lgain, DL_GAIN_N_40DB,
rgain, DL_GAIN_N_40DB);
#define MT6357_DL_GAIN_N_40DB_REG (DL_GAIN_N_40DB << 7 | DL_GAIN_N_40DB)
DL_GAIN_N_40DB);
DL_GAIN_N_40DB);
regmap_write(priv->regmap, MT6358_ZCD_CON3, DL_GAIN_N_40DB);
#define DL_GAIN_N_40DB_REG (DL_GAIN_N_40DB << 7 | DL_GAIN_N_40DB)
reg_idx == DL_GAIN_N_40DB;
regmap_write(priv->regmap, MT6359_ZCD_CON3, DL_GAIN_N_40DB);
regmap_write(priv->regmap, MT6359_ZCD_CON1, DL_GAIN_N_40DB);
reg_idx == DL_GAIN_N_40DB;
#define DL_GAIN_N_40DB_REG (DL_GAIN_N_40DB << 7 | DL_GAIN_N_40DB)