DIV_ROUND_DOWN_ULL
hw_ip.dram_size = DIV_ROUND_DOWN_ULL(dram_available_size, prop->dram_page_size) *
DIV_ROUND_DOWN_ULL(vaddr - prop->dram_base_address,
page_id = DIV_ROUND_DOWN_ULL(abs_phys_addr, dram_page_size);
return DIV_ROUND_DOWN_ULL(prescaled, reg);
rate_div = DIV_ROUND_DOWN_ULL(parent_rate * 1000, rate);
down = DIV_ROUND_DOWN_ULL((u64)parent_rate, rate);
DIV_ROUND_DOWN_ULL(exclusion_ranges[i].start, HZ_PER_MHZ);
tx_byte_period = DIV_ROUND_DOWN_ULL((u64)NSEC_PER_SEC * 8,
max_n = DIV_ROUND_DOWN_ULL((u64)fin, MHZ(2));
return DIV_ROUND_DOWN_ULL(mul_u32_u32(max_link_rate * 10 * max_lanes,
ret.full = DIV_ROUND_DOWN_ULL(mul_u32_u32(link_rate * link_lane_count,
return DIV_ROUND_DOWN_ULL(tmp, dst);
vblank_start = DIV_ROUND_DOWN_ULL(
DIV_ROUND_DOWN_ULL(scaled_vco_div_refclk1, (curve_0_interpolated *
DIV_ROUND_DOWN_ULL(curve_1_interpolated, CURVE0_MULTIPLIER)));
DIV64_U64_ROUND_CLOSEST(DIV_ROUND_DOWN_ULL(adjusted_vco_clk1, curve_2_scaled1),
(curve_2_scaled_int * DIV_ROUND_DOWN_ULL(curve_0_interpolated,
DIV_ROUND_DOWN_ULL(1000000000000ULL, 55));
vco_div_refclk_integer = DIV_ROUND_DOWN_ULL(vco_clk, refclk_postscalar);
vco_div_refclk_fracn = DIV_ROUND_DOWN_ULL(vco_clk_do_div << 32, refclk_postscalar);
vco_div_refclk_float = vco_clk * DIV_ROUND_DOWN_ULL(1000000000000ULL, refclk_postscalar);
curve_1_interpolated = DIV_ROUND_DOWN_ULL(curve_1_interpolated, CURVE1_MULTIPLIER);
curve_2_scaled1 = DIV_ROUND_DOWN_ULL(temp, 16000);
curve_2_scaled2 = DIV_ROUND_DOWN_ULL(temp, 160);
scaled_vco_div_refclk1 = 112008301 * DIV_ROUND_DOWN_ULL(vco_div_refclk_float, 100000);
bpl = DIV_ROUND_DOWN_ULL(bpl, 1000000); /* microseconds */
bpl = DIV_ROUND_DOWN_ULL(bpl, 1000000); /* seconds */
hdmi_tx_div = DIV_ROUND_DOWN_ULL(vclk_freq, dac_freq);
venc_div = DIV_ROUND_DOWN_ULL(vclk_freq, venc_freq);
pll_freq = DIV_ROUND_DOWN_ULL(pll_freq, 2);
return DIV_ROUND_DOWN_ULL(pll_freq, XTAL_FREQ);
if (mode->vdisplay > DIV_ROUND_DOWN_ULL(bochs->fb_size, pitch))
DIV_ROUND_DOWN_ULL(rlimit(RLIMIT_MEMLOCK), PAGE_SIZE);
u32 clk_period = DIV_ROUND_DOWN_ULL(1000000000000ULL,
u32 clk_period = DIV_ROUND_DOWN_ULL(1000000000000ULL,
t_x = DIV_ROUND_DOWN_ULL(1000000000000ULL, denali->clk_x_rate);
DIV_ROUND_DOWN_ULL((u64)type->chipsize << 20,
DIV_ROUND_DOWN_ULL((u64)type->chipsize << 20,
*first = DIV_ROUND_DOWN_ULL(start, bank_size);
*last = DIV_ROUND_DOWN_ULL(start + len - 1, bank_size);
DIV_ROUND_DOWN_ULL((IDPF_CTLQ_MAX_BUF_LEN - IDPF_RX_PTYPE_HDR_SZ), \
DIV_ROUND_DOWN_ULL(stats->tx_unicast, stats->tx_cnt) : 0;
DIV_ROUND_DOWN_ULL(stats->rx_unicast, stats->rx_cnt) : 0;
tas->instant_txpwr = DIV_ROUND_DOWN_ULL(linear, cur_idx);
linear = DIV_ROUND_DOWN_ULL(tas->total_txpwr, tas->window_size * PERCENT);
div = DIV_ROUND_DOWN_ULL(div, NSEC_PER_SEC);
div = DIV_ROUND_DOWN_ULL(div, NSEC_PER_SEC);
duty_cycle = DIV_ROUND_DOWN_ULL(state->duty_cycle * RPI_PWM_MAX_DUTY,
return min_t(u64, DIV_ROUND_DOWN_ULL(period_or_duty_cycle, 1 << (2 * prescale)),
(DIV_ROUND_DOWN_ULL((duty_cycle), NSEC_PER_SEC / SL28CPLD_PWM_CLK))
priv->rcdev.nr_resets = DIV_ROUND_DOWN_ULL(resource_size(res),
DIV_ROUND_DOWN_ULL((unsigned long long)(ll) + (d) - 1, (d))
curr_stats->cpe_ratio = DIV_ROUND_DOWN_ULL(
DIV_ROUND_DOWN_ULL(objoff, l->stripe_unit);
pcm512x->real_pll = DIV_ROUND_DOWN_ULL((u64)K * pllin_rate, 10000 * P);