arch/sh/kernel/cpu/sh4a/clock-sh7343.c

110

[DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

142

[MSTP028] = MSTP(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

194

CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

113

[DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

192

CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

115

[DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

142

[HWBLK_URAM] = SH_CLK_MSTP32(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

178

CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

116

[DIV4_U] = DIV4(FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

203

CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),

arch/sh/kernel/cpu/sh4a/clock-sh7785.c

128

CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),

arch/sh/kernel/cpu/sh4a/clock-sh7785.c

76

[DIV4_U] = DIV4(24, 0x000c, CLK_ENABLE_ON_INIT),