arch/sh/kernel/cpu/sh4a/clock-sh7343.c

116

[DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

200

CLKDEV_CON_ID("siub_clk", &div4_clks[DIV4_SIUB]),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

119

[DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

198

CLKDEV_CON_ID("siub_clk", &div4_clks[DIV4_SIUB]),

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

132

[DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

185

CLKDEV_CON_ID("siub_clk", &div4_reparent_clks[DIV4_SIUB]),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

133

[DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x0dbf, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

210

CLKDEV_CON_ID("siub_clk", &div4_reparent_clks[DIV4_SIUB]),