Symbol: DIV4_SH
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
111
[DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
195
CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
114
[DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
145
[MSTP028] = MSTP(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
193
CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
116
[DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
179
CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
117
[DIV4_SH] = DIV4(FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
146
[HWBLK_L2C] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
151
[HWBLK_SHYWAY] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 20, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
168
[HWBLK_MERAM] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 0, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
173
[HWBLK_ATAPI] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR2, 28, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
204
CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
155
[DIV4_SH] = DIV4(FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
208
[HWBLK_L2C] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
212
[HWBLK_SHYWAY] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 20, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
248
[HWBLK_2DDMAC] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR2, 10, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
269
CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
arch/sh/kernel/cpu/sh4a/clock-sh7757.c
109
CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
arch/sh/kernel/cpu/sh4a/clock-sh7757.c
71
[DIV4_SH] = DIV4(12, 0x00a0, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
127
CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
75
[DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
135
CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
75
[DIV4_SH] = DIV4(20, 0x0002, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-shx3.c
110
CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
arch/sh/kernel/cpu/sh4a/clock-shx3.c
69
[DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT),