Symbol: DIV4_P
arch/sh/kernel/cpu/sh2a/clock-sh7264.c
100
[MSTP32] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 2, 0), /* ADC */
arch/sh/kernel/cpu/sh2a/clock-sh7264.c
112
CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
arch/sh/kernel/cpu/sh2a/clock-sh7264.c
84
[DIV4_P] = DIV4(FRQCR, 0, 0x78, CLK_ENABLE_REG_16BIT),
arch/sh/kernel/cpu/sh2a/clock-sh7264.c
93
[MSTP77] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR7, 7, 0), /* SCIF */
arch/sh/kernel/cpu/sh2a/clock-sh7264.c
94
[MSTP74] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR7, 4, 0), /* VDC */
arch/sh/kernel/cpu/sh2a/clock-sh7264.c
95
[MSTP72] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR7, 2, 0), /* CMT */
arch/sh/kernel/cpu/sh2a/clock-sh7264.c
96
[MSTP60] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR6, 0, 0), /* USB */
arch/sh/kernel/cpu/sh2a/clock-sh7264.c
97
[MSTP35] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 6, 0), /* MTU2 */
arch/sh/kernel/cpu/sh2a/clock-sh7264.c
98
[MSTP34] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 4, 0), /* SDHI0 */
arch/sh/kernel/cpu/sh2a/clock-sh7264.c
99
[MSTP33] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 3, 0), /* SDHI1 */
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
114
[DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
144
[MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
145
[MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
146
[MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
147
[MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
148
[MSTP019] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
149
[MSTP017] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
150
[MSTP015] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
153
[MSTP011] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
154
[MSTP010] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
155
[MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
156
[MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
157
[MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
158
[MSTP004] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
159
[MSTP003] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 3, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
160
[MSTP002] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
161
[MSTP001] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 1, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
163
[MSTP109] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
164
[MSTP108] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 8, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
166
[MSTP225] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 25, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
167
[MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
168
[MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
169
[MSTP217] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 17, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
170
[MSTP216] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 16, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
172
[MSTP213] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 13, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
173
[MSTP212] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 12, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
174
[MSTP211] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 11, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
198
CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
117
[DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
147
[MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
148
[MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
149
[MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
150
[MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
151
[MSTP019] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
152
[MSTP017] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
153
[MSTP015] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
156
[MSTP011] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
157
[MSTP010] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
158
[MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
159
[MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
160
[MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
161
[MSTP002] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
162
[MSTP001] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 1, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
164
[MSTP109] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
166
[MSTP227] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 27, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
167
[MSTP226] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 26, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
168
[MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
169
[MSTP223] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 23, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
170
[MSTP222] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 22, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
171
[MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
172
[MSTP217] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 17, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
173
[MSTP211] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 11, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
196
CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
119
[DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
144
[HWBLK_TMU] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
147
[HWBLK_FLCTL] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
148
[HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
149
[HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 6, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
150
[HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
152
[HWBLK_IIC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
155
[HWBLK_SDHI] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 18, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
157
[HWBLK_USBF] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 11, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
166
[HWBLK_LCDC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 0, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
182
CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
120
[DIV4_P] = DIV4(FRQCR, 0, 0x0dbf, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
152
[HWBLK_HUDI] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
154
[HWBLK_TMU0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
158
[HWBLK_TMU1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
159
[HWBLK_FLCTL] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
160
[HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
161
[HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
162
[HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
170
[HWBLK_IIC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
174
[HWBLK_ADC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 27, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
176
[HWBLK_IRDA] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
207
CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
157
[DIV4_P] = DIV4(FRQCRA, 0, 0x2f7c, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
210
[HWBLK_INTC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
213
[HWBLK_HUDI] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
215
[HWBLK_TMU0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
219
[HWBLK_TMU1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
220
[HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
221
[HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
222
[HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
231
[HWBLK_IIC0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
232
[HWBLK_IIC1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 8, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
238
[HWBLK_IRDA] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
271
CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
126
[MSTP030] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 30, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
127
[MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
128
[MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
129
[MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
130
[MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
131
[MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
132
[MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
133
[MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
134
[MSTP019] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
135
[MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
136
[MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
137
[MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
138
[MSTP012] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 12, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
139
[MSTP011] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
140
[MSTP010] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
141
[MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
142
[MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
143
[MSTP007] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
146
[MSTP115] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 15, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
147
[MSTP114] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 14, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
148
[MSTP111] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 11, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
149
[MSTP109] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
150
[MSTP108] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 8, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
151
[MSTP107] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 7, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
152
[MSTP106] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 6, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
153
[MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 3, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
154
[MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 0, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
157
[MSTP331] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 31, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
158
[MSTP330] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 30, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
159
[MSTP323] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 23, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
160
[MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
161
[MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
162
[MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
163
[MSTP319] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 19, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
164
[MSTP318] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 18, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
165
[MSTP317] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 17, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
166
[MSTP316] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 16, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
167
[MSTP315] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 15, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
168
[MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 14, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
169
[MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 13, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
170
[MSTP312] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 12, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
171
[MSTP304] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 4, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
172
[MSTP303] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 3, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
173
[MSTP302] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 2, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
174
[MSTP301] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 1, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
175
[MSTP300] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 0, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
189
CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
78
[DIV4_P] = DIV4(FRQMR1, 0, 0x0140, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7757.c
108
CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
arch/sh/kernel/cpu/sh4a/clock-sh7757.c
70
[DIV4_P] = DIV4(0, 0x2800, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7757.c
85
[MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7757.c
86
[MSTP000] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 0, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7757.c
89
[MSTP127] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 27, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7757.c
90
[MSTP114] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 14, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7757.c
91
[MSTP113] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 13, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7757.c
92
[MSTP112] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 12, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7757.c
93
[MSTP111] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 11, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7757.c
94
[MSTP110] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 10, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7757.c
95
[MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 3, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7757.c
96
[MSTP102] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 2, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7757.c
99
[MSTP220] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 20, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
100
[MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
101
[MSTP013] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 13, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
102
[MSTP012] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 12, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
103
[MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
104
[MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
105
[MSTP003] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 3, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
106
[MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
122
CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
70
[DIV4_P] = DIV4(0, 0x0f80, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
91
[MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
92
[MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
93
[MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
94
[MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
95
[MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
96
[MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
97
[MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
98
[MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
99
[MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
100
[MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
101
[MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
102
[MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
103
[MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
104
[MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
105
[MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
106
[MSTP011] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
107
[MSTP010] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
108
[MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
109
[MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
110
[MSTP005] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
111
[MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
112
[MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
131
CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
71
[DIV4_P] = DIV4(0, 0x0b40, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
92
[MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
93
[MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
94
[MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
95
[MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
96
[MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
97
[MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
98
[MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
99
[MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
arch/sh/kernel/cpu/sh4a/clock-shx3.c
106
CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
arch/sh/kernel/cpu/sh4a/clock-shx3.c
65
[DIV4_P] = DIV4(0, 0x0f80, 0),
arch/sh/kernel/cpu/sh4a/clock-shx3.c
83
[MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
arch/sh/kernel/cpu/sh4a/clock-shx3.c
84
[MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
arch/sh/kernel/cpu/sh4a/clock-shx3.c
85
[MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
arch/sh/kernel/cpu/sh4a/clock-shx3.c
86
[MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
arch/sh/kernel/cpu/sh4a/clock-shx3.c
87
[MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
arch/sh/kernel/cpu/sh4a/clock-shx3.c
88
[MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
arch/sh/kernel/cpu/sh4a/clock-shx3.c
89
[MSTP003] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 3, 0),
arch/sh/kernel/cpu/sh4a/clock-shx3.c
90
[MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
arch/sh/kernel/cpu/sh4a/clock-shx3.c
91
[MSTP001] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 1, 0),
arch/sh/kernel/cpu/sh4a/clock-shx3.c
92
[MSTP000] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 0, 0),