arch/sh/kernel/cpu/sh2a/clock-sh7264.c

111

CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),

arch/sh/kernel/cpu/sh2a/clock-sh7264.c

82

[DIV4_I] = DIV4(FRQCR, 4, 0x7, CLK_ENABLE_REG_16BIT

arch/sh/kernel/cpu/sh2a/clock-sh7269.c

110

[DIV4_I] = DIV4(FRQCR, 8, 0xB, CLK_ENABLE_REG_16BIT

arch/sh/kernel/cpu/sh2a/clock-sh7269.c

146

CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

109

[DIV4_I] = DIV4(FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

139

[MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

140

[MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

141

[MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

193

CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

112

[DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

142

[MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

143

[MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

144

[MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

191

CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

114

[DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

177

CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

115

[DIV4_I] = DIV4(FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

143

[HWBLK_TLB] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

144

[HWBLK_IC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

145

[HWBLK_OC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

147

[HWBLK_ILMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 27, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

148

[HWBLK_FPU] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 24, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

149

[HWBLK_INTC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 22, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

153

[HWBLK_UBC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 17, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

202

CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

154

[DIV4_I] = DIV4(FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

203

[HWBLK_TLB] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

204

[HWBLK_IC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

205

[HWBLK_OC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

207

[HWBLK_ILMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 27, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

209

[HWBLK_FPU] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 24, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

214

[HWBLK_UBC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 17, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

268

CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),

arch/sh/kernel/cpu/sh4a/clock-sh7734.c

184

CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),

arch/sh/kernel/cpu/sh4a/clock-sh7734.c

73

[DIV4_I] = DIV4(FRQMR1, 28, 0x0003, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7757.c

110

CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),

arch/sh/kernel/cpu/sh4a/clock-sh7757.c

72

[DIV4_I] = DIV4(20, 0x0004, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7785.c

129

CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),

arch/sh/kernel/cpu/sh4a/clock-sh7785.c

77

[DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7786.c

136

CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),

arch/sh/kernel/cpu/sh4a/clock-sh7786.c

76

[DIV4_I] = DIV4(28, 0x0006, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-shx3.c

111

CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),

arch/sh/kernel/cpu/sh4a/clock-shx3.c

70

[DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),