Symbol: DIV4_DDR
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
125
CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
73
[DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
133
CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
73
[DIV4_DDR] = DIV4(12, 0x0002, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-shx3.c
108
CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
arch/sh/kernel/cpu/sh4a/clock-shx3.c
67
[DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT),