arch/sh/kernel/cpu/sh2a/clock-sh7269.c

112

[DIV4_B] = DIV4(FRQCR, 4, 0xA, CLK_ENABLE_REG_16BIT

arch/sh/kernel/cpu/sh2a/clock-sh7269.c

147

CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

112

[DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

143

[MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

175

[MSTP208] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 8, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

176

[MSTP206] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

177

[MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

178

[MSTP204] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 4, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

179

[MSTP203] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 3, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

180

[MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

181

[MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

182

[MSTP200] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 0, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

196

CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

115

[DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

146

[MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

174

[MSTP207] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 7, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

175

[MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

176

[MSTP204] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 4, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

177

[MSTP203] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 3, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

178

[MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

179

[MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

180

[MSTP200] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 0, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

194

CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

117

[DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

143

[HWBLK_XYMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

158

[HWBLK_2DG] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 9, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

159

[HWBLK_SIU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 8, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

160

[HWBLK_JPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

161

[HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

162

[HWBLK_BEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

163

[HWBLK_CEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

164

[HWBLK_VEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 2, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

165

[HWBLK_VPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 1, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

180

CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

118

[DIV4_B] = DIV4(FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

150

[HWBLK_DMAC0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 21, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

157

[HWBLK_DMAC1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 12, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

163

[HWBLK_SCIF3] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 6, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

164

[HWBLK_SCIF4] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 5, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

165

[HWBLK_SCIF5] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 4, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

166

[HWBLK_MSIOF0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 2, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

167

[HWBLK_MSIOF1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 1, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

175

[HWBLK_TPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 25, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

177

[HWBLK_TSIF] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 22, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

178

[HWBLK_ICB] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 21, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

179

[HWBLK_SDHI0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 18, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

180

[HWBLK_SDHI1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 17, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

182

[HWBLK_USB] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 11, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

183

[HWBLK_2DG] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 10, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

184

[HWBLK_SIU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 8, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

185

[HWBLK_VEU2H1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

186

[HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

187

[HWBLK_BEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

188

[HWBLK_CEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

189

[HWBLK_VEU2H0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 2, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

190

[HWBLK_VPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 1, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

191

[HWBLK_LCDC] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 0, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

205

CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

156

[DIV4_B] = DIV4(FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

206

[HWBLK_RSMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 28, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

211

[HWBLK_DMAC0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 21, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

218

[HWBLK_DMAC1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 12, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

223

[HWBLK_SCIF3] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 6, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

224

[HWBLK_SCIF4] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 5, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

225

[HWBLK_SCIF5] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 4, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

226

[HWBLK_MSIOF0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 2, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

227

[HWBLK_MSIOF1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 1, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

234

[HWBLK_MMC] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 29, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

235

[HWBLK_ETHER] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 28, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

236

[HWBLK_ATAPI] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 26, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

237

[HWBLK_TPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 25, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

239

[HWBLK_TSIF] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 22, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

240

[HWBLK_USB1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 21, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

241

[HWBLK_USB0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 20, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

242

[HWBLK_2DG] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 19, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

243

[HWBLK_SDHI0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 18, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

244

[HWBLK_SDHI1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 17, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

245

[HWBLK_VEU1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 15, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

246

[HWBLK_CEU1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 13, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

247

[HWBLK_BEU1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 12, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

249

[HWBLK_SPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 9, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

250

[HWBLK_JPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

251

[HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

252

[HWBLK_BEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

253

[HWBLK_CEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

254

[HWBLK_VEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 2, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

255

[HWBLK_VPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 1, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

256

[HWBLK_LCDC] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 0, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

270

CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),

arch/sh/kernel/cpu/sh4a/clock-sh7734.c

187

CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),

arch/sh/kernel/cpu/sh4a/clock-sh7734.c

75

[DIV4_B] = DIV4(FRQMR1, 16, 0x0140, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7785.c

126

CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),

arch/sh/kernel/cpu/sh4a/clock-sh7785.c

74

[DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7786.c

134

CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),

arch/sh/kernel/cpu/sh4a/clock-sh7786.c

74

[DIV4_B] = DIV4(16, 0x0360, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-shx3.c

109

CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),

arch/sh/kernel/cpu/sh4a/clock-shx3.c

68

[DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT),