arch/sh/kernel/cpu/sh2a/clock-sh7264.c

82

[DIV4_I] = DIV4(FRQCR, 4, 0x7, CLK_ENABLE_REG_16BIT

arch/sh/kernel/cpu/sh2a/clock-sh7264.c

84

[DIV4_P] = DIV4(FRQCR, 0, 0x78, CLK_ENABLE_REG_16BIT),

arch/sh/kernel/cpu/sh2a/clock-sh7269.c

110

[DIV4_I] = DIV4(FRQCR, 8, 0xB, CLK_ENABLE_REG_16BIT

arch/sh/kernel/cpu/sh2a/clock-sh7269.c

112

[DIV4_B] = DIV4(FRQCR, 4, 0xA, CLK_ENABLE_REG_16BIT

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

109

[DIV4_I] = DIV4(FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

110

[DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

111

[DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

112

[DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

113

[DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

114

[DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

115

[DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

116

[DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

112

[DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

113

[DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

114

[DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

115

[DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

116

[DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

117

[DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

118

[DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

119

[DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

114

[DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

115

[DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

116

[DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

117

[DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

118

[DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

119

[DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

125

[DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x1fff, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

131

[DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

132

[DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

115

[DIV4_I] = DIV4(FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

116

[DIV4_U] = DIV4(FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

117

[DIV4_SH] = DIV4(FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

118

[DIV4_B] = DIV4(FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

119

[DIV4_B3] = DIV4(FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

120

[DIV4_P] = DIV4(FRQCR, 0, 0x0dbf, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

126

[DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x0dbf, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

132

[DIV4_SIUA] = DIV4(SCLKACR, 0, 0x0dbf, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

133

[DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x0dbf, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

154

[DIV4_I] = DIV4(FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

155

[DIV4_SH] = DIV4(FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

156

[DIV4_B] = DIV4(FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

157

[DIV4_P] = DIV4(FRQCRA, 0, 0x2f7c, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

158

[DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7734.c

73

[DIV4_I] = DIV4(FRQMR1, 28, 0x0003, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7734.c

74

[DIV4_S] = DIV4(FRQMR1, 20, 0x000C, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7734.c

75

[DIV4_B] = DIV4(FRQMR1, 16, 0x0140, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7734.c

76

[DIV4_M] = DIV4(FRQMR1, 12, 0x0004, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7734.c

77

[DIV4_S1] = DIV4(FRQMR1, 4, 0x0030, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7734.c

78

[DIV4_P] = DIV4(FRQMR1, 0, 0x0140, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7757.c

70

[DIV4_P] = DIV4(0, 0x2800, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7757.c

71

[DIV4_SH] = DIV4(12, 0x00a0, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7757.c

72

[DIV4_I] = DIV4(20, 0x0004, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7785.c

70

[DIV4_P] = DIV4(0, 0x0f80, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7785.c

71

[DIV4_DU] = DIV4(4, 0x0ff0, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7785.c

72

[DIV4_GA] = DIV4(8, 0x0030, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7785.c

73

[DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7785.c

74

[DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7785.c

75

[DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7785.c

76

[DIV4_U] = DIV4(24, 0x000c, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7785.c

77

[DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7786.c

71

[DIV4_P] = DIV4(0, 0x0b40, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7786.c

72

[DIV4_DU] = DIV4(4, 0x0010, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7786.c

73

[DIV4_DDR] = DIV4(12, 0x0002, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7786.c

74

[DIV4_B] = DIV4(16, 0x0360, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7786.c

75

[DIV4_SH] = DIV4(20, 0x0002, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7786.c

76

[DIV4_I] = DIV4(28, 0x0006, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-shx3.c

65

[DIV4_P] = DIV4(0, 0x0f80, 0),

arch/sh/kernel/cpu/sh4a/clock-shx3.c

66

[DIV4_SHA] = DIV4(4, 0x0ff0, 0),

arch/sh/kernel/cpu/sh4a/clock-shx3.c

67

[DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-shx3.c

68

[DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-shx3.c

69

[DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-shx3.c

70

[DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),

drivers/video/fbdev/platinumfb.h

169

{{ 30, 0 + DIV4 }, { 56, 7 + DIV2 }}

drivers/video/fbdev/platinumfb.h

181

{{ 122, 7 + DIV4 }, { 62, 9 + DIV2 }}

drivers/video/fbdev/platinumfb.h

193

{{ 26, 0 + DIV4 }, { 42, 6 + DIV2 }}

drivers/video/fbdev/platinumfb.h

205

{{ 54, 3 + DIV4 }, { 95, 1 + DIV8 }}

drivers/video/fbdev/platinumfb.h

217

{{ 54, 3 + DIV4 }, { 88, 1 + DIV8 }}

drivers/video/fbdev/platinumfb.h

241

{{ 30, 0 + DIV4 }, { 56, 7 + DIV2 }}

drivers/video/fbdev/platinumfb.h

253

{{ 99, 4 + DIV8 }, { 42, 5 + DIV4 }}

drivers/video/fbdev/platinumfb.h

265

{{ 26, 0 + DIV8 }, { 14, 2 + DIV4 }}