DISPC_MGR_FLD_GO
[DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
[DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
[DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 },
[DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 },
return mgr_fld_read(dispc, channel, DISPC_MGR_FLD_GO) == 1;
mgr_fld_write(dispc, channel, DISPC_MGR_FLD_GO, 1);
[DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
[DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
[DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 },
[DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 },
return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);