arch/arm/mach-omap2/display.c

338

omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);

arch/arm/mach-omap2/display.c

360

while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=

drivers/gpu/drm/omapdrm/dss/dispc.c

3359

DUMPREG(dispc, DISPC_IRQSTATUS);

drivers/gpu/drm/omapdrm/dss/dispc.c

3618

return dispc_read_reg(dispc, DISPC_IRQSTATUS);

drivers/gpu/drm/omapdrm/dss/dispc.c

3623

dispc_write_reg(dispc, DISPC_IRQSTATUS, mask);

drivers/gpu/drm/tidss/tidss_dispc.c

742

dispc_write(dispc, DISPC_IRQSTATUS,

drivers/gpu/drm/tidss/tidss_dispc.c

743

dispc_read(dispc, DISPC_IRQSTATUS));

drivers/gpu/drm/tidss/tidss_dispc.c

867

dispc_write(dispc, DISPC_IRQSTATUS, dispc_read(dispc, DISPC_IRQSTATUS));

drivers/gpu/drm/tidss/tidss_dispc.c

870

dispc_read(dispc, DISPC_IRQSTATUS);

drivers/gpu/drm/tidss/tidss_dispc_regs.h

67

#define DISPC_IRQSTATUS REG(DISPC_IRQSTATUS)

drivers/video/fbdev/omap2/omapfb/dss/dispc.c

3395

DUMPREG(DISPC_IRQSTATUS);

drivers/video/fbdev/omap2/omapfb/dss/dispc.c

3649

return dispc_read_reg(DISPC_IRQSTATUS);

drivers/video/fbdev/omap2/omapfb/dss/dispc.c

3655

dispc_write_reg(DISPC_IRQSTATUS, mask);