DISPC_CONTROL
v = omap_hwmod_read(oh, DISPC_CONTROL);
v = omap_hwmod_read(oh, DISPC_CONTROL);
omap_hwmod_write(v, oh, DISPC_CONTROL);
[DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
[DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
[DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
[DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
[DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
REG_FLD_MOD(dispc, DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
REG_FLD_MOD(dispc, DISPC_CONTROL, enable ? 1 : 0, 28, 28);
REG_FLD_MOD(dispc, DISPC_CONTROL, enable ? 1 : 0, 27, 27);
[DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
[DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
l = dispc_read_reg(dispc, DISPC_CONTROL);
dispc_write_reg(dispc, DISPC_CONTROL, l);
REG_FLD_MOD(dispc, DISPC_CONTROL,
DUMPREG(dispc, DISPC_CONTROL);
[DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
[DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
[DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
[DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
[DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
[DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
[DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
const bool need_lock = rfld.reg == DISPC_CONTROL || rfld.reg == DISPC_CONFIG;
REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
l = dispc_read_reg(DISPC_CONTROL);
dispc_write_reg(DISPC_CONTROL, l);
DUMPREG(DISPC_CONTROL);