drivers/edac/i5400_edac.c

1097

for (slot_row = 0; slot_row < DIMMS_PER_CHANNEL; slot_row++) {

drivers/edac/i5400_edac.c

1122

for (slot_row = 0; slot_row < DIMMS_PER_CHANNEL; slot_row++)

drivers/edac/i5400_edac.c

1139

for (slot_row = 0; slot_row < DIMMS_PER_CHANNEL; slot_row++)

drivers/edac/i5400_edac.c

1283

layers[2].size = DIMMS_PER_CHANNEL;

drivers/edac/i5400_edac.c

1296

pvt->maxdimmperch = DIMMS_PER_CHANNEL;

drivers/edac/i5400_edac.c

342

u16 b0_mtr[DIMMS_PER_CHANNEL]; /* Memory Technlogy Reg */

drivers/edac/i5400_edac.c

346

u16 b1_mtr[DIMMS_PER_CHANNEL]; /* Memory Technlogy Reg */

drivers/edac/i5400_edac.c

351

struct i5400_dimm_info dimm_info[DIMMS_PER_CHANNEL][MAX_CHANNELS];

drivers/edac/i5400_edac.c

873

if (n >= DIMMS_PER_CHANNEL) {