arch/mips/alchemy/common/dbdma.c

102

{ AU1550_DSCR_CMD0_MAC0_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },

arch/mips/alchemy/common/dbdma.c

106

{ AU1550_DSCR_CMD0_MAC1_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },

arch/mips/alchemy/common/dbdma.c

113

{ AU1200_DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },

arch/mips/alchemy/common/dbdma.c

115

{ AU1200_DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x11200004, 0, 0 },

arch/mips/alchemy/common/dbdma.c

126

{ AU1200_DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 },

arch/mips/alchemy/common/dbdma.c

128

{ AU1200_DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 4, 8, 0x10680000, 0, 0 },

arch/mips/alchemy/common/dbdma.c

132

{ AU1200_DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 },

arch/mips/alchemy/common/dbdma.c

134

{ AU1200_DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x11a0001c, 0, 0 },

arch/mips/alchemy/common/dbdma.c

137

{ AU1200_DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x11b0001c, 0, 0 },

arch/mips/alchemy/common/dbdma.c

153

{ AU1300_DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x10100004, 0, 0 },

arch/mips/alchemy/common/dbdma.c

155

{ AU1300_DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x10101004, 0, 0 },

arch/mips/alchemy/common/dbdma.c

157

{ AU1300_DSCR_CMD0_UART2_TX, DEV_FLAGS_OUT, 0, 8, 0x10102004, 0, 0 },

arch/mips/alchemy/common/dbdma.c

159

{ AU1300_DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x10103004, 0, 0 },

arch/mips/alchemy/common/dbdma.c

162

{ AU1300_DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 },

arch/mips/alchemy/common/dbdma.c

164

{ AU1300_DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 8, 8, 0x10601000, 0, 0 },

arch/mips/alchemy/common/dbdma.c

168

{ AU1300_DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 },

arch/mips/alchemy/common/dbdma.c

170

{ AU1300_DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0001c, 0, 0 },

arch/mips/alchemy/common/dbdma.c

172

{ AU1300_DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0101c, 0, 0 },

arch/mips/alchemy/common/dbdma.c

174

{ AU1300_DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0201c, 0, 0 },

arch/mips/alchemy/common/dbdma.c

176

{ AU1300_DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0301c, 0, 0 },

arch/mips/alchemy/common/dbdma.c

182

{ AU1300_DSCR_CMD0_SDMS_TX2, DEV_FLAGS_OUT, 4, 8, 0x10602000, 0, 0 },

arch/mips/alchemy/common/dbdma.c

381

if (dtp->dev_flags & DEV_FLAGS_OUT) { /* Destination out fifo */

arch/mips/alchemy/common/dbdma.c

493

if (dtp->dev_flags & DEV_FLAGS_OUT)

arch/mips/alchemy/common/dbdma.c

548

if (dtp->dev_flags & DEV_FLAGS_OUT) {

arch/mips/alchemy/common/dbdma.c

68

{ AU1550_DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },

arch/mips/alchemy/common/dbdma.c

70

{ AU1550_DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x11400004, 0, 0 },

arch/mips/alchemy/common/dbdma.c

81

{ AU1550_DSCR_CMD0_USBDEV_TX0, DEV_FLAGS_OUT, 4, 8, 0x10200004, 0, 0 },

arch/mips/alchemy/common/dbdma.c

82

{ AU1550_DSCR_CMD0_USBDEV_TX1, DEV_FLAGS_OUT, 4, 8, 0x10200008, 0, 0 },

arch/mips/alchemy/common/dbdma.c

83

{ AU1550_DSCR_CMD0_USBDEV_TX2, DEV_FLAGS_OUT, 4, 8, 0x1020000c, 0, 0 },

arch/mips/alchemy/common/dbdma.c

88

{ AU1550_DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 },

arch/mips/alchemy/common/dbdma.c

90

{ AU1550_DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 0, 0x11b0001c, 0, 0 },

arch/mips/alchemy/common/dbdma.c

92

{ AU1550_DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 0, 0x10a0001c, 0, 0 },

arch/mips/alchemy/common/dbdma.c

94

{ AU1550_DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 0, 0x10b0001c, 0, 0 },