DFS
ath_dbg(common, DFS, "DFS enabled at freq %d\n",
ath_dbg(common, DFS, "HT40: datalen=%d, num_fft_packets=%d\n",
ath_dbg(common, DFS, "not enough packets for chirp\n");
ath_dbg(common, DFS, "fixing datalen by 2\n");
ath_dbg(common, DFS, "HT20: datalen=%d, num_fft_packets=%d\n",
ath_dbg(common, DFS, "not enough packets for chirp\n");
ath_dbg(common, DFS, "bin_max = [%d, %d, %d, %d]\n",
ath_dbg(common, DFS, "CHIRP: invalid delta %d "
ath_dbg(common, DFS, "CHIRP: ddelta %d too high\n",
ath_dbg(common, DFS, "CHIRP - %d: delta=%d, ddelta=%d\n",
ath_dbg(common, DFS,
ath_dbg(common, DFS,
ath_dbg(dpd->common, DFS,
ath_dbg(dpd->common, DFS,
ath_dbg(common, DFS,"Could not set DFS domain to %d", region);
CHECK_AND_PRINT(DFS), eeprom_ch->flags,
CHECK_AND_PRINT_I(DFS),
CHECK_AND_PRINT(DFS),
CHECK_AND_PRINT_I(DFS),
mt76_wr(dev, MT_BBP(DFS, 36), data);
mt76_wr(dev, MT_BBP(DFS, 1), 0xf);
mt76_wr(dev, MT_BBP(DFS, 0), data);
pulse->period = mt76_rr(dev, MT_BBP(DFS, 19));
pulse->w1 = mt76_rr(dev, MT_BBP(DFS, 20));
pulse->w2 = mt76_rr(dev, MT_BBP(DFS, 23));
pulse->burst = mt76_rr(dev, MT_BBP(DFS, 22));
data = mt76_rr(dev, MT_BBP(DFS, 37));
data = mt76_rr(dev, MT_BBP(DFS, 37));
data = mt76_rr(dev, MT_BBP(DFS, 37));
engine_mask = mt76_rr(dev, MT_BBP(DFS, 1));
mt76_wr(dev, MT_BBP(DFS, 1), 0xf);
mt76_wr(dev, MT_BBP(DFS, 2), data);
mt76_wr(dev, MT_BBP(DFS, 3), data);
mt76_wr(dev, MT_BBP(DFS, 0), i);
mt76_wr(dev, MT_BBP(DFS, 4), data);
mt76_wr(dev, MT_BBP(DFS, 5), data);
mt76_wr(dev, MT_BBP(DFS, 7), radar_specs[i].t_low);
mt76_wr(dev, MT_BBP(DFS, 9), radar_specs[i].t_high);
mt76_wr(dev, MT_BBP(DFS, 11), radar_specs[i].b_low);
mt76_wr(dev, MT_BBP(DFS, 13), radar_specs[i].b_high);
mt76_wr(dev, MT_BBP(DFS, 14), data);
mt76_wr(dev, MT_BBP(DFS, 15), data);
mt76_wr(dev, MT_BBP(DFS, 17), radar_specs[i].event_expiration);
mt76_wr(dev, MT_BBP(DFS, 30), radar_specs[i].pwr_jmp);
mt76_wr(dev, MT_BBP(DFS, 1), 0xf);
mt76_wr(dev, MT_BBP(DFS, 36), 0x3);
mt76_wr(dev, MT_BBP(DFS, 0), MT_DFS_CH_EN << 16);
mt76_wr(dev, MT_BBP(DFS, 31), dfs_r31);
mt76_wr(dev, MT_BBP(DFS, 32), 0x00040071);
mt76_wr(dev, MT_BBP(DFS, 0), 0);
mt76_wr(dev, MT_BBP(DFS, 0), MT_DFS_CH_EN << 16);
mt76_wr(dev, MT_BBP(DFS, 0), 0);
mt76_wr(dev, MT_BBP(DFS, 1), 0xf);
np->rv_ctest5 |= DFS; /* Dma Fifo Size */
ctest5 = (np->rv_ctest5 & DFS) ? INB (nc_ctest5) : 0;
if (ctest5 & DFS)
if (dfifo & (DFS << 16))
np->rv_ctest5 |= DFS; /* Dma Fifo Size */