drivers/fpga/dfl.c

1309

v = readq(binfo->ioaddr + DFH);

drivers/fpga/dfl.c

1362

v = readq(binfo->ioaddr + ofst + DFH);

drivers/fpga/dfl.c

1403

v = readq(binfo->ioaddr + start - binfo->start + DFH);

drivers/fpga/dfl.h

123

#define FME_HDR_DFH DFH

drivers/fpga/dfl.h

164

#define PORT_HDR_DFH DFH

drivers/fpga/dfl.h

477

u64 v = readq(base + DFH);

drivers/fpga/dfl.h

485

u64 v = readq(base + DFH);

drivers/fpga/dfl.h

493

return (u8)FIELD_GET(DFH_REVISION, readq(base + DFH));