arch/mips/alchemy/common/dbdma.c

101

{ AU1550_DSCR_CMD0_MAC0_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },

arch/mips/alchemy/common/dbdma.c

105

{ AU1550_DSCR_CMD0_MAC1_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },

arch/mips/alchemy/common/dbdma.c

114

{ AU1200_DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },

arch/mips/alchemy/common/dbdma.c

116

{ AU1200_DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x11200000, 0, 0 },

arch/mips/alchemy/common/dbdma.c

127

{ AU1200_DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 },

arch/mips/alchemy/common/dbdma.c

129

{ AU1200_DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 4, 8, 0x10680004, 0, 0 },

arch/mips/alchemy/common/dbdma.c

131

{ AU1200_DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 },

arch/mips/alchemy/common/dbdma.c

135

{ AU1200_DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x11a0001c, 0, 0 },

arch/mips/alchemy/common/dbdma.c

138

{ AU1200_DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x11b0001c, 0, 0 },

arch/mips/alchemy/common/dbdma.c

141

{ AU1200_DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 32, 0x14004020, 0, 0 },

arch/mips/alchemy/common/dbdma.c

142

{ AU1200_DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 32, 0x14004040, 0, 0 },

arch/mips/alchemy/common/dbdma.c

143

{ AU1200_DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 32, 0x14004060, 0, 0 },

arch/mips/alchemy/common/dbdma.c

146

{ AU1200_DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },

arch/mips/alchemy/common/dbdma.c

154

{ AU1300_DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x10100000, 0, 0 },

arch/mips/alchemy/common/dbdma.c

156

{ AU1300_DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x10101000, 0, 0 },

arch/mips/alchemy/common/dbdma.c

158

{ AU1300_DSCR_CMD0_UART2_RX, DEV_FLAGS_IN, 0, 8, 0x10102000, 0, 0 },

arch/mips/alchemy/common/dbdma.c

160

{ AU1300_DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x10103000, 0, 0 },

arch/mips/alchemy/common/dbdma.c

163

{ AU1300_DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 },

arch/mips/alchemy/common/dbdma.c

165

{ AU1300_DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 8, 8, 0x10601004, 0, 0 },

arch/mips/alchemy/common/dbdma.c

167

{ AU1300_DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 },

arch/mips/alchemy/common/dbdma.c

171

{ AU1300_DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x10a0001c, 0, 0 },

arch/mips/alchemy/common/dbdma.c

173

{ AU1300_DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x10a0101c, 0, 0 },

arch/mips/alchemy/common/dbdma.c

175

{ AU1300_DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 16, 0x10a0201c, 0, 0 },

arch/mips/alchemy/common/dbdma.c

177

{ AU1300_DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 16, 0x10a0301c, 0, 0 },

arch/mips/alchemy/common/dbdma.c

180

{ AU1300_DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },

arch/mips/alchemy/common/dbdma.c

183

{ AU1300_DSCR_CMD0_SDMS_RX2, DEV_FLAGS_IN, 4, 8, 0x10602004, 0, 0 },

arch/mips/alchemy/common/dbdma.c

377

if (stp->dev_flags & DEV_FLAGS_IN) { /* Source in fifo */

arch/mips/alchemy/common/dbdma.c

491

if (stp->dev_flags & DEV_FLAGS_IN)

arch/mips/alchemy/common/dbdma.c

517

if (stp->dev_flags & DEV_FLAGS_IN) {

arch/mips/alchemy/common/dbdma.c

69

{ AU1550_DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },

arch/mips/alchemy/common/dbdma.c

71

{ AU1550_DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x11400000, 0, 0 },

arch/mips/alchemy/common/dbdma.c

80

{ AU1550_DSCR_CMD0_USBDEV_RX0, DEV_FLAGS_IN, 4, 8, 0x10200000, 0, 0 },

arch/mips/alchemy/common/dbdma.c

84

{ AU1550_DSCR_CMD0_USBDEV_RX3, DEV_FLAGS_IN, 4, 8, 0x10200010, 0, 0 },

arch/mips/alchemy/common/dbdma.c

85

{ AU1550_DSCR_CMD0_USBDEV_RX4, DEV_FLAGS_IN, 4, 8, 0x10200014, 0, 0 },

arch/mips/alchemy/common/dbdma.c

89

{ AU1550_DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 },

arch/mips/alchemy/common/dbdma.c

91

{ AU1550_DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 },

arch/mips/alchemy/common/dbdma.c

93

{ AU1550_DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 0, 0x10a0001c, 0, 0 },

arch/mips/alchemy/common/dbdma.c

95

{ AU1550_DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 0, 0x10b0001c, 0, 0 },