DESC_SIZE
dma_addr_t end = beg + (ring_count * DESC_SIZE);
addr += DESC_SIZE;
return beg + DESC_SIZE - 1;
dma_addr_t end = beg + (ring_count * DESC_SIZE);
addr += DESC_SIZE;
#define DESC_RING_SIZE (DESC_RING_COUNT * DESC_SIZE)
cb->bd_addr = priv->rx_bds + i * DESC_SIZE;
#define TDMA_PORT_SIZE DESC_SIZE /* two 32-bits words */
desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
__le32 *desc = dev->tx_descs + (i * DESC_SIZE);
memset(dev->tx_descs, 0, NR_TX_DESC * DESC_SIZE * 4);
first_desc = dev->tx_descs + (free_idx * DESC_SIZE);
volatile __le32 *desc = dev->tx_descs + (free_idx * DESC_SIZE);
desc[DESC_LINK] = cpu_to_le32(dev->tx_phy_descs + (free_idx * DESC_SIZE * 4));
dev->tx_idx = txdp / (DESC_SIZE * 4);
desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
memset(dev->tx_descs, 0, 4 * NR_TX_DESC * DESC_SIZE);
dev->tx_descs[(i * DESC_SIZE) + DESC_LINK]
+ ((i+1) % NR_TX_DESC) * DESC_SIZE * 4);
4 * DESC_SIZE * NR_TX_DESC,
4 * DESC_SIZE * NR_RX_DESC,
dma_free_coherent(&pci_dev->dev, 4 * DESC_SIZE * NR_TX_DESC,
dma_free_coherent(&pci_dev->dev, 4 * DESC_SIZE * NR_RX_DESC,
dma_free_coherent(&dev->pci_dev->dev, 4 * DESC_SIZE * NR_TX_DESC,
dma_free_coherent(&dev->pci_dev->dev, 4 * DESC_SIZE * NR_RX_DESC,
(4 * DESC_SIZE * dev->rx_info.next_rx),
sg = dev->rx_info.descs + (next_empty * DESC_SIZE);
dev->rx_info.descs[((NR_RX_DESC + next_empty - 1) % NR_RX_DESC) * DESC_SIZE] = cpu_to_le32(dev->rx_info.phy_descs + (next_empty * DESC_SIZE * 4));
build_rx_desc(dev, dev->rx_info.descs + (DESC_SIZE * i), 0, 0, CMDSTS_OWN, 0);
(dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_rx)),
(dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_empty))
desc = info->descs + (DESC_SIZE * next_rx);
info->next_rx_desc = info->descs + (DESC_SIZE * next_rx);
desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);