drivers/net/ethernet/hisilicon/hip04_eth.c

389

priv->reg_inten = DEF_INT_MASK;

drivers/net/ethernet/hisilicon/hip04_eth.c

399

priv->reg_inten &= ~(DEF_INT_MASK);

drivers/net/ethernet/hisilicon/hip04_eth.c

561

writel_relaxed(DEF_INT_MASK & ~RCV_INT,

drivers/net/ethernet/hisilicon/hip04_eth.c

671

writel_relaxed(DEF_INT_MASK, priv->base + PPE_RINT);

drivers/net/ethernet/hisilicon/hip04_eth.c

688

writel_relaxed(DEF_INT_MASK & ~RCV_INT, priv->base + PPE_INTEN);

drivers/net/ethernet/hisilicon/hip04_eth.c

705

writel_relaxed(DEF_INT_MASK & ~RCV_INT, priv->base + PPE_INTEN);

drivers/net/ethernet/hisilicon/hisi_femac.c

316

writel(ints & DEF_INT_MASK,

drivers/net/ethernet/hisilicon/hisi_femac.c

318

} while (ints & DEF_INT_MASK);

drivers/net/ethernet/hisilicon/hisi_femac.c

322

hisi_femac_irq_enable(priv, DEF_INT_MASK &

drivers/net/ethernet/hisilicon/hisi_femac.c

337

if (likely(ints & DEF_INT_MASK)) {

drivers/net/ethernet/hisilicon/hisi_femac.c

338

writel(ints & DEF_INT_MASK,

drivers/net/ethernet/hisilicon/hisi_femac.c

340

hisi_femac_irq_disable(priv, DEF_INT_MASK);

drivers/net/ethernet/hisilicon/hisi_femac.c

477

hisi_femac_irq_enable(priv, IRQ_ENA_ALL | IRQ_ENA_PORT0 | DEF_INT_MASK);

drivers/net/ethernet/hisilicon/hix5hd2_gmac.c

410

writel_relaxed(DEF_INT_MASK, priv->base + ENA_PMU_INT);

drivers/net/ethernet/hisilicon/hix5hd2_gmac.c

659

} while (ints & DEF_INT_MASK);

drivers/net/ethernet/hisilicon/hix5hd2_gmac.c

676

if (likely(ints & DEF_INT_MASK)) {