arch/mips/dec/setup.c

103

int cpu_fpu_mask = DEC_CPU_IRQ_MASK(DEC_CPU_INR_FPU);

arch/mips/dec/setup.c

203

{ { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_BUS) },

arch/mips/dec/setup.c

205

{ { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_RTC) },

arch/mips/dec/setup.c

207

{ { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_DZ11) },

arch/mips/dec/setup.c

209

{ { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_SII) },

arch/mips/dec/setup.c

211

{ { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_LANCE) },

arch/mips/dec/setup.c

280

{ { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_BUS) },

arch/mips/dec/setup.c

282

{ { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_RTC) },

arch/mips/dec/setup.c

284

{ { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_DZ11) },

arch/mips/dec/setup.c

286

{ { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_SII) },

arch/mips/dec/setup.c

355

{ { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_BUS) },

arch/mips/dec/setup.c

357

{ { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_RTC) },

arch/mips/dec/setup.c

359

{ { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_CASCADE) },

arch/mips/dec/setup.c

452

{ { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_CASCADE) },

arch/mips/dec/setup.c

454

{ { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC2) },

arch/mips/dec/setup.c

456

{ { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC1) },

arch/mips/dec/setup.c

458

{ { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC0) },

arch/mips/dec/setup.c

553

{ { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_BUS) },

arch/mips/dec/setup.c

555

{ { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_RTC) },

arch/mips/dec/setup.c

557

{ { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_CASCADE) },

arch/mips/dec/setup.c

650

{ { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_BUS) },

arch/mips/dec/setup.c

652

{ { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_RTC) },

arch/mips/dec/setup.c

654

{ { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_CASCADE) },