drivers/accel/amdxdna/npu1_regs.c

100

DEFINE_BAR_OFFSET(SMU_ARG_REG, NPU1_SMU, MPNPU_PUB_SCRATCH7),

drivers/accel/amdxdna/npu1_regs.c

101

DEFINE_BAR_OFFSET(SMU_INTR_REG, NPU1_SMU, MPNPU_PUB_PWRMGMT_INTR),

drivers/accel/amdxdna/npu1_regs.c

102

DEFINE_BAR_OFFSET(SMU_RESP_REG, NPU1_SMU, MPNPU_PUB_SCRATCH6),

drivers/accel/amdxdna/npu1_regs.c

103

DEFINE_BAR_OFFSET(SMU_OUT_REG, NPU1_SMU, MPNPU_PUB_SCRATCH7),

drivers/accel/amdxdna/npu1_regs.c

85

DEFINE_BAR_OFFSET(MBOX_CHANN_OFF, NPU1_SRAM, MPNPU_SRAM_X2I_MAILBOX_0),

drivers/accel/amdxdna/npu1_regs.c

86

DEFINE_BAR_OFFSET(FW_ALIVE_OFF, NPU1_SRAM, MPNPU_SRAM_I2X_MAILBOX_15),

drivers/accel/amdxdna/npu1_regs.c

89

DEFINE_BAR_OFFSET(PSP_CMD_REG, NPU1_PSP, MPNPU_PUB_SCRATCH2),

drivers/accel/amdxdna/npu1_regs.c

90

DEFINE_BAR_OFFSET(PSP_ARG0_REG, NPU1_PSP, MPNPU_PUB_SCRATCH3),

drivers/accel/amdxdna/npu1_regs.c

91

DEFINE_BAR_OFFSET(PSP_ARG1_REG, NPU1_PSP, MPNPU_PUB_SCRATCH4),

drivers/accel/amdxdna/npu1_regs.c

92

DEFINE_BAR_OFFSET(PSP_ARG2_REG, NPU1_PSP, MPNPU_PUB_SCRATCH9),

drivers/accel/amdxdna/npu1_regs.c

93

DEFINE_BAR_OFFSET(PSP_INTR_REG, NPU1_PSP, MPNPU_PUB_SEC_INTR),

drivers/accel/amdxdna/npu1_regs.c

94

DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU1_PSP, MPNPU_PUB_SCRATCH2),

drivers/accel/amdxdna/npu1_regs.c

95

DEFINE_BAR_OFFSET(PSP_RESP_REG, NPU1_PSP, MPNPU_PUB_SCRATCH3),

drivers/accel/amdxdna/npu1_regs.c

96

DEFINE_BAR_OFFSET(PSP_PWAITMODE_REG, NPU1_PSP, MPNPU_PWAITMODE),

drivers/accel/amdxdna/npu1_regs.c

99

DEFINE_BAR_OFFSET(SMU_CMD_REG, NPU1_SMU, MPNPU_PUB_SCRATCH5),

drivers/accel/amdxdna/npu4_regs.c

111

DEFINE_BAR_OFFSET(MBOX_CHANN_OFF, NPU4_SRAM, MPNPU_SRAM_X2I_MAILBOX_0),

drivers/accel/amdxdna/npu4_regs.c

112

DEFINE_BAR_OFFSET(FW_ALIVE_OFF, NPU4_SRAM, MPNPU_SRAM_X2I_MAILBOX_15),

drivers/accel/amdxdna/npu4_regs.c

115

DEFINE_BAR_OFFSET(PSP_CMD_REG, NPU4_PSP, MP0_C2PMSG_123),

drivers/accel/amdxdna/npu4_regs.c

116

DEFINE_BAR_OFFSET(PSP_ARG0_REG, NPU4_REG, MPNPU_PUB_SCRATCH3),

drivers/accel/amdxdna/npu4_regs.c

117

DEFINE_BAR_OFFSET(PSP_ARG1_REG, NPU4_REG, MPNPU_PUB_SCRATCH4),

drivers/accel/amdxdna/npu4_regs.c

118

DEFINE_BAR_OFFSET(PSP_ARG2_REG, NPU4_REG, MPNPU_PUB_SCRATCH9),

drivers/accel/amdxdna/npu4_regs.c

119

DEFINE_BAR_OFFSET(PSP_INTR_REG, NPU4_PSP, MP0_C2PMSG_73),

drivers/accel/amdxdna/npu4_regs.c

120

DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU4_PSP, MP0_C2PMSG_123),

drivers/accel/amdxdna/npu4_regs.c

121

DEFINE_BAR_OFFSET(PSP_RESP_REG, NPU4_REG, MPNPU_PUB_SCRATCH3),

drivers/accel/amdxdna/npu4_regs.c

122

DEFINE_BAR_OFFSET(PSP_PWAITMODE_REG, NPU4_REG, MPNPU_PWAITMODE),

drivers/accel/amdxdna/npu4_regs.c

125

DEFINE_BAR_OFFSET(SMU_CMD_REG, NPU4_SMU, MP1_C2PMSG_0),

drivers/accel/amdxdna/npu4_regs.c

126

DEFINE_BAR_OFFSET(SMU_ARG_REG, NPU4_SMU, MP1_C2PMSG_60),

drivers/accel/amdxdna/npu4_regs.c

127

DEFINE_BAR_OFFSET(SMU_INTR_REG, NPU4_SMU, MMNPU_APERTURE4_BASE),

drivers/accel/amdxdna/npu4_regs.c

128

DEFINE_BAR_OFFSET(SMU_RESP_REG, NPU4_SMU, MP1_C2PMSG_61),

drivers/accel/amdxdna/npu4_regs.c

129

DEFINE_BAR_OFFSET(SMU_OUT_REG, NPU4_SMU, MP1_C2PMSG_60),

drivers/accel/amdxdna/npu5_regs.c

76

DEFINE_BAR_OFFSET(MBOX_CHANN_OFF, NPU5_SRAM, MPNPU_SRAM_X2I_MAILBOX_0),

drivers/accel/amdxdna/npu5_regs.c

77

DEFINE_BAR_OFFSET(FW_ALIVE_OFF, NPU5_SRAM, MPNPU_SRAM_X2I_MAILBOX_15),

drivers/accel/amdxdna/npu5_regs.c

80

DEFINE_BAR_OFFSET(PSP_CMD_REG, NPU5_PSP, MP0_C2PMSG_123),

drivers/accel/amdxdna/npu5_regs.c

81

DEFINE_BAR_OFFSET(PSP_ARG0_REG, NPU5_REG, MPNPU_PUB_SCRATCH3),

drivers/accel/amdxdna/npu5_regs.c

82

DEFINE_BAR_OFFSET(PSP_ARG1_REG, NPU5_REG, MPNPU_PUB_SCRATCH4),

drivers/accel/amdxdna/npu5_regs.c

83

DEFINE_BAR_OFFSET(PSP_ARG2_REG, NPU5_REG, MPNPU_PUB_SCRATCH9),

drivers/accel/amdxdna/npu5_regs.c

84

DEFINE_BAR_OFFSET(PSP_INTR_REG, NPU5_PSP, MP0_C2PMSG_73),

drivers/accel/amdxdna/npu5_regs.c

85

DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU5_PSP, MP0_C2PMSG_123),

drivers/accel/amdxdna/npu5_regs.c

86

DEFINE_BAR_OFFSET(PSP_RESP_REG, NPU5_REG, MPNPU_PUB_SCRATCH3),

drivers/accel/amdxdna/npu5_regs.c

87

DEFINE_BAR_OFFSET(PSP_PWAITMODE_REG, NPU5_REG, MPNPU_PWAITMODE),

drivers/accel/amdxdna/npu5_regs.c

90

DEFINE_BAR_OFFSET(SMU_CMD_REG, NPU5_SMU, MP1_C2PMSG_0),

drivers/accel/amdxdna/npu5_regs.c

91

DEFINE_BAR_OFFSET(SMU_ARG_REG, NPU5_SMU, MP1_C2PMSG_60),

drivers/accel/amdxdna/npu5_regs.c

92

DEFINE_BAR_OFFSET(SMU_INTR_REG, NPU5_SMU, MMNPU_APERTURE4_BASE),

drivers/accel/amdxdna/npu5_regs.c

93

DEFINE_BAR_OFFSET(SMU_RESP_REG, NPU5_SMU, MP1_C2PMSG_61),

drivers/accel/amdxdna/npu5_regs.c

94

DEFINE_BAR_OFFSET(SMU_OUT_REG, NPU5_SMU, MP1_C2PMSG_60),

drivers/accel/amdxdna/npu6_regs.c

76

DEFINE_BAR_OFFSET(MBOX_CHANN_OFF, NPU6_SRAM, MPNPU_SRAM_X2I_MAILBOX_0),

drivers/accel/amdxdna/npu6_regs.c

77

DEFINE_BAR_OFFSET(FW_ALIVE_OFF, NPU6_SRAM, MPNPU_SRAM_X2I_MAILBOX_15),

drivers/accel/amdxdna/npu6_regs.c

80

DEFINE_BAR_OFFSET(PSP_CMD_REG, NPU6_PSP, MP0_C2PMSG_123),

drivers/accel/amdxdna/npu6_regs.c

81

DEFINE_BAR_OFFSET(PSP_ARG0_REG, NPU6_REG, MPNPU_PUB_SCRATCH3),

drivers/accel/amdxdna/npu6_regs.c

82

DEFINE_BAR_OFFSET(PSP_ARG1_REG, NPU6_REG, MPNPU_PUB_SCRATCH4),

drivers/accel/amdxdna/npu6_regs.c

83

DEFINE_BAR_OFFSET(PSP_ARG2_REG, NPU6_REG, MPNPU_PUB_SCRATCH9),

drivers/accel/amdxdna/npu6_regs.c

84

DEFINE_BAR_OFFSET(PSP_INTR_REG, NPU6_PSP, MP0_C2PMSG_73),

drivers/accel/amdxdna/npu6_regs.c

85

DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU6_PSP, MP0_C2PMSG_123),

drivers/accel/amdxdna/npu6_regs.c

86

DEFINE_BAR_OFFSET(PSP_RESP_REG, NPU6_REG, MPNPU_PUB_SCRATCH3),

drivers/accel/amdxdna/npu6_regs.c

87

DEFINE_BAR_OFFSET(PSP_PWAITMODE_REG, NPU6_REG, MPNPU_PWAITMODE),

drivers/accel/amdxdna/npu6_regs.c

90

DEFINE_BAR_OFFSET(SMU_CMD_REG, NPU6_SMU, MP1_C2PMSG_0),

drivers/accel/amdxdna/npu6_regs.c

91

DEFINE_BAR_OFFSET(SMU_ARG_REG, NPU6_SMU, MP1_C2PMSG_60),

drivers/accel/amdxdna/npu6_regs.c

92

DEFINE_BAR_OFFSET(SMU_INTR_REG, NPU6_SMU, MMNPU_APERTURE4_BASE),

drivers/accel/amdxdna/npu6_regs.c

93

DEFINE_BAR_OFFSET(SMU_RESP_REG, NPU6_SMU, MP1_C2PMSG_61),

drivers/accel/amdxdna/npu6_regs.c

94

DEFINE_BAR_OFFSET(SMU_OUT_REG, NPU6_SMU, MP1_C2PMSG_60),