arch/mips/dec/setup.c

166

[DEC_IRQ_DZ11] = DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11),

arch/mips/dec/setup.c

169

[DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),

arch/mips/dec/setup.c

172

[DEC_IRQ_LANCE] = DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE),

arch/mips/dec/setup.c

173

[DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN01_CPU_INR_BUS),

arch/mips/dec/setup.c

175

[DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC),

arch/mips/dec/setup.c

178

[DEC_IRQ_SII] = DEC_CPU_IRQ_NR(KN01_CPU_INR_SII),

arch/mips/dec/setup.c

183

[DEC_IRQ_VIDEO] = DEC_CPU_IRQ_NR(KN01_CPU_INR_VIDEO),

arch/mips/dec/setup.c

208

{ .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_BUS) } },

arch/mips/dec/setup.c

210

{ .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC) } },

arch/mips/dec/setup.c

212

{ .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11) } },

arch/mips/dec/setup.c

214

{ .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_SII) } },

arch/mips/dec/setup.c

216

{ .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE) } },

arch/mips/dec/setup.c

243

[DEC_IRQ_DZ11] = DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11),

arch/mips/dec/setup.c

246

[DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),

arch/mips/dec/setup.c

247

[DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN230_CPU_INR_HALT),

arch/mips/dec/setup.c

249

[DEC_IRQ_LANCE] = DEC_CPU_IRQ_NR(KN230_CPU_INR_LANCE),

arch/mips/dec/setup.c

250

[DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN230_CPU_INR_BUS),

arch/mips/dec/setup.c

252

[DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC),

arch/mips/dec/setup.c

255

[DEC_IRQ_SII] = DEC_CPU_IRQ_NR(KN230_CPU_INR_SII),

arch/mips/dec/setup.c

285

{ .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_BUS) } },

arch/mips/dec/setup.c

287

{ .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC) } },

arch/mips/dec/setup.c

289

{ .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11) } },

arch/mips/dec/setup.c

291

{ .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_SII) } },

arch/mips/dec/setup.c

315

[DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02_CPU_INR_CASCADE),

arch/mips/dec/setup.c

321

[DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),

arch/mips/dec/setup.c

325

[DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN02_CPU_INR_BUS),

arch/mips/dec/setup.c

327

[DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC),

arch/mips/dec/setup.c

360

{ .i = DEC_CPU_IRQ_NR(KN02_CPU_INR_BUS) } },

arch/mips/dec/setup.c

362

{ .i = DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC) } },

arch/mips/dec/setup.c

412

[DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_CASCADE),

arch/mips/dec/setup.c

418

[DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),

arch/mips/dec/setup.c

419

[DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_HALT),

arch/mips/dec/setup.c

428

[DEC_IRQ_TC0] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0),

arch/mips/dec/setup.c

429

[DEC_IRQ_TC1] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1),

arch/mips/dec/setup.c

430

[DEC_IRQ_TC2] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2),

arch/mips/dec/setup.c

459

{ .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2) } },

arch/mips/dec/setup.c

461

{ .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1) } },

arch/mips/dec/setup.c

463

{ .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0) } },

arch/mips/dec/setup.c

513

[DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_CASCADE),

arch/mips/dec/setup.c

519

[DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),

arch/mips/dec/setup.c

520

[DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_HALT),

arch/mips/dec/setup.c

523

[DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_BUS),

arch/mips/dec/setup.c

525

[DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC),

arch/mips/dec/setup.c

532

[DEC_IRQ_TIMER] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_TIMER),

arch/mips/dec/setup.c

558

{ .i = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_BUS) } },

arch/mips/dec/setup.c

560

{ .i = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC) } },

arch/mips/dec/setup.c

610

[DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN03_CPU_INR_CASCADE),

arch/mips/dec/setup.c

616

[DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),

arch/mips/dec/setup.c

617

[DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN03_CPU_INR_HALT),

arch/mips/dec/setup.c

620

[DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN03_CPU_INR_BUS),

arch/mips/dec/setup.c

622

[DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC),

arch/mips/dec/setup.c

655

{ .i = DEC_CPU_IRQ_NR(KN03_CPU_INR_BUS) } },

arch/mips/dec/setup.c

657

{ .i = DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC) } },