arch/mips/dec/setup.c

107

int cpu_fpu_mask = DEC_CPU_IRQ_MASK(DEC_CPU_INR_FPU);

arch/mips/dec/setup.c

207

{ { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_BUS) },

arch/mips/dec/setup.c

209

{ { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_RTC) },

arch/mips/dec/setup.c

211

{ { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_DZ11) },

arch/mips/dec/setup.c

213

{ { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_SII) },

arch/mips/dec/setup.c

215

{ { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_LANCE) },

arch/mips/dec/setup.c

284

{ { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_BUS) },

arch/mips/dec/setup.c

286

{ { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_RTC) },

arch/mips/dec/setup.c

288

{ { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_DZ11) },

arch/mips/dec/setup.c

290

{ { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_SII) },

arch/mips/dec/setup.c

359

{ { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_BUS) },

arch/mips/dec/setup.c

361

{ { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_RTC) },

arch/mips/dec/setup.c

363

{ { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_CASCADE) },

arch/mips/dec/setup.c

456

{ { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_CASCADE) },

arch/mips/dec/setup.c

458

{ { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC2) },

arch/mips/dec/setup.c

460

{ { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC1) },

arch/mips/dec/setup.c

462

{ { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC0) },

arch/mips/dec/setup.c

557

{ { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_BUS) },

arch/mips/dec/setup.c

559

{ { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_RTC) },

arch/mips/dec/setup.c

561

{ { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_CASCADE) },

arch/mips/dec/setup.c

654

{ { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_BUS) },

arch/mips/dec/setup.c

656

{ { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_RTC) },

arch/mips/dec/setup.c

658

{ { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_CASCADE) },