drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2456

case DC_SW_LINEAR:

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

638

GRPH_SW_MODE, DC_SW_LINEAR);

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

643

GRPH_ARRAY_MODE, DC_SW_LINEAR);

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

648

GRPH_ARRAY_MODE, DC_SW_LINEAR);

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

165

case DC_SW_LINEAR:

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

258

case DC_SW_LINEAR:

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1261

case DC_SW_LINEAR:

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

337

case DC_SW_LINEAR:

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

527

REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

415

REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

343

REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

565

REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1254

enum swizzle_mode_values swizzle = DC_SW_LINEAR;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1316

tiling_info->gfx9.swizzle = DC_SW_LINEAR;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

406

if (pipe->plane_state && !disable_unbounded_requesting && pipe->plane_state->tiling_info.gfx9.swizzle != DC_SW_LINEAR) {