drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c

176

DC_LOG_DSC("%s FEC at link encoder inst %d",

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1000

DC_LOG_DSC("\tbpp_increment_div %d", dsc_sink_caps->bpp_increment_div);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1001

DC_LOG_DSC("\tbranch_overall_throughput_0_mps %d", dsc_sink_caps->branch_overall_throughput_0_mps);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1002

DC_LOG_DSC("\tbranch_overall_throughput_1_mps %d", dsc_sink_caps->branch_overall_throughput_1_mps);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1003

DC_LOG_DSC("\tbranch_max_line_width %d", dsc_sink_caps->branch_max_line_width);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1004

DC_LOG_DSC("\tis_dp %d", dsc_sink_caps->is_dp);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

972

DC_LOG_DSC("dsc encoder caps:");

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

973

DC_LOG_DSC("\tdsc_version 0x%x", dsc_enc_caps.dsc_version);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

974

DC_LOG_DSC("\tslice_caps 0x%x", dsc_enc_caps.slice_caps.raw);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

975

DC_LOG_DSC("\tlb_bit_depth %d", dsc_enc_caps.lb_bit_depth);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

976

DC_LOG_DSC("\tis_block_pred_supported %d", dsc_enc_caps.is_block_pred_supported);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

977

DC_LOG_DSC("\tcolor_formats 0x%x", dsc_enc_caps.color_formats.raw);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

978

DC_LOG_DSC("\tcolor_depth 0x%x", dsc_enc_caps.color_depth.raw);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

979

DC_LOG_DSC("\tmax_total_throughput_mps %d", dsc_enc_caps.max_total_throughput_mps);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

980

DC_LOG_DSC("\tmax_slice_width %d", dsc_enc_caps.max_slice_width);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

981

DC_LOG_DSC("\tbpp_increment_div %d", dsc_enc_caps.bpp_increment_div);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

987

DC_LOG_DSC("dsc decoder caps:");

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

988

DC_LOG_DSC("\tis_dsc_supported %d", dsc_sink_caps->is_dsc_supported);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

989

DC_LOG_DSC("\tdsc_version 0x%x", dsc_sink_caps->dsc_version);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

990

DC_LOG_DSC("\trc_buffer_size %d", dsc_sink_caps->rc_buffer_size);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

991

DC_LOG_DSC("\tslice_caps1 0x%x", dsc_sink_caps->slice_caps1.raw);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

992

DC_LOG_DSC("\tslice_caps2 0x%x", dsc_sink_caps->slice_caps2.raw);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

993

DC_LOG_DSC("\tlb_bit_depth %d", dsc_sink_caps->lb_bit_depth);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

994

DC_LOG_DSC("\tis_block_pred_supported %d", dsc_sink_caps->is_block_pred_supported);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

995

DC_LOG_DSC("\tedp_max_bits_per_pixel %d", dsc_sink_caps->edp_max_bits_per_pixel);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

996

DC_LOG_DSC("\tcolor_formats 0x%x", dsc_sink_caps->color_formats.raw);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

997

DC_LOG_DSC("\tthroughput_mode_0_mps %d", dsc_sink_caps->throughput_mode_0_mps);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

998

DC_LOG_DSC("\tthroughput_mode_1_mps %d", dsc_sink_caps->throughput_mode_1_mps);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

999

DC_LOG_DSC("\tmax_slice_width %d", dsc_sink_caps->max_slice_width);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

182

DC_LOG_DSC("\tnum_slices_h %d", config->dc_dsc_cfg.num_slices_h);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

183

DC_LOG_DSC("\tnum_slices_v %d", config->dc_dsc_cfg.num_slices_v);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

184

DC_LOG_DSC("\tbits_per_pixel %d (%d.%04d)",

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

188

DC_LOG_DSC("\tcolor_depth %d", config->color_depth);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

197

DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc->inst);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

201

DC_LOG_DSC("programming DSC Picture Parameter Set (PPS):");

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

216

DC_LOG_DSC("Getting packed DSC PPS for DSC Config:");

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

218

DC_LOG_DSC("DSC Picture Parameter Set (PPS):");

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

235

DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

240

DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already enabled!", dsc->inst, enabled_opp_pipe);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

258

DC_LOG_DSC("disable DSC %d", dsc->inst);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

262

DC_LOG_DSC("DSC %d already disabled!", dsc->inst);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

283

DC_LOG_DSC("disconnect DSC %d", dsc->inst);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

295

DC_LOG_DSC("\tdsc_version_major %d", pps->dsc_version_major);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

296

DC_LOG_DSC("\tdsc_version_minor %d", pps->dsc_version_minor);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

297

DC_LOG_DSC("\tbits_per_component %d", pps->bits_per_component);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

298

DC_LOG_DSC("\tline_buf_depth %d", pps->line_buf_depth);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

299

DC_LOG_DSC("\tblock_pred_enable %d", pps->block_pred_enable);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

300

DC_LOG_DSC("\tconvert_rgb %d", pps->convert_rgb);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

301

DC_LOG_DSC("\tsimple_422 %d", pps->simple_422);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

302

DC_LOG_DSC("\tvbr_enable %d", pps->vbr_enable);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

303

DC_LOG_DSC("\tbits_per_pixel %d (%d.%04d)", bits_per_pixel, bits_per_pixel / 16, ((bits_per_pixel % 16) * 10000) / 16);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

304

DC_LOG_DSC("\tpic_height %d", pps->pic_height);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

305

DC_LOG_DSC("\tpic_width %d", pps->pic_width);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

306

DC_LOG_DSC("\tslice_height %d", pps->slice_height);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

307

DC_LOG_DSC("\tslice_width %d", pps->slice_width);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

308

DC_LOG_DSC("\tslice_chunk_size %d", pps->slice_chunk_size);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

309

DC_LOG_DSC("\tinitial_xmit_delay %d", pps->initial_xmit_delay);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

310

DC_LOG_DSC("\tinitial_dec_delay %d", pps->initial_dec_delay);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

311

DC_LOG_DSC("\tinitial_scale_value %d", pps->initial_scale_value);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

312

DC_LOG_DSC("\tscale_increment_interval %d", pps->scale_increment_interval);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

313

DC_LOG_DSC("\tscale_decrement_interval %d", pps->scale_decrement_interval);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

314

DC_LOG_DSC("\tfirst_line_bpg_offset %d", pps->first_line_bpg_offset);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

315

DC_LOG_DSC("\tnfl_bpg_offset %d", pps->nfl_bpg_offset);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

316

DC_LOG_DSC("\tslice_bpg_offset %d", pps->slice_bpg_offset);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

317

DC_LOG_DSC("\tinitial_offset %d", pps->initial_offset);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

318

DC_LOG_DSC("\tfinal_offset %d", pps->final_offset);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

319

DC_LOG_DSC("\tflatness_min_qp %d", pps->flatness_min_qp);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

320

DC_LOG_DSC("\tflatness_max_qp %d", pps->flatness_max_qp);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

322

DC_LOG_DSC("\tnative_420 %d", pps->native_420);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

323

DC_LOG_DSC("\tnative_422 %d", pps->native_422);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

324

DC_LOG_DSC("\tsecond_line_bpg_offset %d", pps->second_line_bpg_offset);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

325

DC_LOG_DSC("\tnsl_bpg_offset %d", pps->nsl_bpg_offset);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

326

DC_LOG_DSC("\tsecond_line_offset_adj %d", pps->second_line_offset_adj);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

327

DC_LOG_DSC("\trc_model_size %d", pps->rc_model_size);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

328

DC_LOG_DSC("\trc_edge_factor %d", pps->rc_edge_factor);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

329

DC_LOG_DSC("\trc_quant_incr_limit0 %d", pps->rc_quant_incr_limit0);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

330

DC_LOG_DSC("\trc_quant_incr_limit1 %d", pps->rc_quant_incr_limit1);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

331

DC_LOG_DSC("\trc_tgt_offset_high %d", pps->rc_tgt_offset_high);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

332

DC_LOG_DSC("\trc_tgt_offset_low %d", pps->rc_tgt_offset_low);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

335

DC_LOG_DSC("\trc_buf_thresh[%d] %d", i, pps->rc_buf_thresh[i]);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

338

DC_LOG_DSC("\trc_range_parameters[%d].range_min_qp %d", i, pps->rc_range_params[i].range_min_qp);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

339

DC_LOG_DSC("\trc_range_parameters[%d].range_max_qp %d", i, pps->rc_range_params[i].range_max_qp);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

340

DC_LOG_DSC("\trc_range_parameters[%d].range_bpg_offset %d", i, pps->rc_range_params[i].range_bpg_offset);

drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

86

DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe);

drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

99

DC_LOG_DSC("ERROR: DSC %d at opp pipe %u already enabled!", dsc->inst, enabled_opp_pipe);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

136

DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc->inst);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

140

DC_LOG_DSC("programming DSC Picture Parameter Set (PPS):");

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

152

DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

157

DC_LOG_DSC("ERROR: DSC %d at opp pipe %u already enabled!", dsc->inst, enabled_opp_pipe);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

175

DC_LOG_DSC("disable DSC %d", dsc->inst);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

179

DC_LOG_DSC("DSC %d already disabled!", dsc->inst);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

200

DC_LOG_DSC("disconnect DSC %d", dsc->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

128

DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

90

DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

97

DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1057

DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1064

DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1098

DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

93

DC_LOG_DSC("%s DSC power gate for inst %d", power_gate ? "enable" : "disable", dsc_inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

349

DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

356

DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

386

DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

680

DC_LOG_DSC("\tbytes_per_pixel 0x%08x (%d.%07d)",

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

682

DC_LOG_DSC("\tis_pixel_format_444 %d", config->is_pixel_format_444);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

683

DC_LOG_DSC("\tslice_width %d", config->slice_width);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

780

DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_enc->id);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

794

DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.hpo_frl_stream_enc->id);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

808

DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

913

DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.stream_enc->id);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

929

DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.hpo_frl_stream_enc->id);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

2051

DC_LOG_DSC("DSC branch decoder capability is read at link %d", link->link_index);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

2052

DC_LOG_DSC("\tBRANCH_OVERALL_THROUGHPUT_0 = 0x%02x",

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

2054

DC_LOG_DSC("\tBRANCH_OVERALL_THROUGHPUT_1 = 0x%02x",

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

2056

DC_LOG_DSC("\tBRANCH_MAX_LINE_WIDTH 0x%02x",

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

2076

DC_LOG_DSC("Clear DSC SUPPORT for USB4 link(%d) in TBT3 compatibility mode", link->link_index);