drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4727

int_params.irq_source < DC_IRQ_SOURCE_HPD1 ||

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

495

for (src = DC_IRQ_SOURCE_HPD1; src <= DC_IRQ_SOURCE_HPD6RX; src++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

557

for (src = DC_IRQ_SOURCE_HPD1; src <= DC_IRQ_SOURCE_HPD6; src++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

682

return DC_IRQ_SOURCE_HPD1;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

907

for (i = DC_IRQ_SOURCE_HPD1; i <= DC_IRQ_SOURCE_HPD6RX; i++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

940

irq_type = dc_link->irq_source_hpd - DC_IRQ_SOURCE_HPD1;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

998

irq_type = dc_link->irq_source_hpd - DC_IRQ_SOURCE_HPD1;

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

390

return (enum dc_irq_source)(DC_IRQ_SOURCE_HPD1 +

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

375

return DC_IRQ_SOURCE_HPD1;

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

90

[DC_IRQ_SOURCE_HPD1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

91

[DC_IRQ_SOURCE_HPD1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c

308

return DC_IRQ_SOURCE_HPD1;

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

102

return DC_IRQ_SOURCE_HPD1;

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

191

[DC_IRQ_SOURCE_HPD1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

103

return DC_IRQ_SOURCE_HPD1;

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

196

[DC_IRQ_SOURCE_HPD1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

140

[DC_IRQ_SOURCE_HPD1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

66

return DC_IRQ_SOURCE_HPD1;

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

104

return DC_IRQ_SOURCE_HPD1;

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

218

[DC_IRQ_SOURCE_HPD1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

112

return DC_IRQ_SOURCE_HPD1;

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

225

[DC_IRQ_SOURCE_HPD1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

214

[DC_IRQ_SOURCE_HPD1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

99

return DC_IRQ_SOURCE_HPD1;

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

138

[DC_IRQ_SOURCE_HPD1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

66

return DC_IRQ_SOURCE_HPD1;

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

101

return DC_IRQ_SOURCE_HPD1;

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

213

[DC_IRQ_SOURCE_HPD1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

103

return DC_IRQ_SOURCE_HPD1;

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

215

[DC_IRQ_SOURCE_HPD1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

108

return DC_IRQ_SOURCE_HPD1;

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

220

[DC_IRQ_SOURCE_HPD1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

102

return DC_IRQ_SOURCE_HPD1;

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

224

[DC_IRQ_SOURCE_HPD1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

100

return DC_IRQ_SOURCE_HPD1;

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

212

IRQ_REG_ENTRY(DC_IRQ_SOURCE_HPD1, HPD, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

215

REG_STRUCT[DC_IRQ_SOURCE_HPD1 + reg_num].funcs = &hpd_irq_info_funcs;\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

216

REG_STRUCT[DC_IRQ_SOURCE_HPD1 + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

191

IRQ_REG_ENTRY(DC_IRQ_SOURCE_HPD1, HPD, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

194

REG_STRUCT[DC_IRQ_SOURCE_HPD1 + reg_num].funcs = &hpd_irq_info_funcs;\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

195

REG_STRUCT[DC_IRQ_SOURCE_HPD1 + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

79

return DC_IRQ_SOURCE_HPD1;

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

190

IRQ_REG_ENTRY(DC_IRQ_SOURCE_HPD1, HPD, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

193

REG_STRUCT[DC_IRQ_SOURCE_HPD1 + reg_num].funcs = &hpd_irq_info_funcs;\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

194

REG_STRUCT[DC_IRQ_SOURCE_HPD1 + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

78

return DC_IRQ_SOURCE_HPD1;

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

204

[DC_IRQ_SOURCE_HPD1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

82

return DC_IRQ_SOURCE_HPD1;

drivers/gpu/drm/amd/display/dc/irq/dcn42/irq_service_dcn42.c

202

[DC_IRQ_SOURCE_HPD1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn42/irq_service_dcn42.c

80

return DC_IRQ_SOURCE_HPD1;

drivers/gpu/drm/amd/display/dc/link/link_factory.c

640

link->irq_source_hpd = DC_IRQ_SOURCE_HPD1 + link->hpd_src;

drivers/gpu/drm/amd/display/dc/link/protocols/link_hpd.c

150

case DC_IRQ_SOURCE_HPD1: