drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1530

case DC_IP_REQUEST_CNTL:

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4095

seq_state->steps[*seq_state->num_steps].func = DC_IP_REQUEST_CNTL;

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h

1045

HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h

254

SR(DC_IP_REQUEST_CNTL)

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h

319

SR(DC_IP_REQUEST_CNTL)

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h

369

SR(DC_IP_REQUEST_CNTL)

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h

477

SR(DC_IP_REQUEST_CNTL), \

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h

537

SR(DC_IP_REQUEST_CNTL), \

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h

597

uint32_t DC_IP_REQUEST_CNTL;

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h

833

HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h

898

HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh)

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h

938

HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh)

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h

990

HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1061

if (REG(DC_IP_REQUEST_CNTL)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1062

REG_SET(DC_IP_REQUEST_CNTL, 0,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1071

REG_SET(DC_IP_REQUEST_CNTL, 0,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1088

REG_SET(DC_IP_REQUEST_CNTL, 0,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1092

REG_SET(DC_IP_REQUEST_CNTL, 0,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1117

REG_SET(DC_IP_REQUEST_CNTL, 0,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1121

REG_SET(DC_IP_REQUEST_CNTL, 0,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1539

if (REG(DC_IP_REQUEST_CNTL)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1540

REG_SET(DC_IP_REQUEST_CNTL, 0,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1552

REG_SET(DC_IP_REQUEST_CNTL, 0,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1286

if (REG(DC_IP_REQUEST_CNTL)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1287

REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1289

REG_SET(DC_IP_REQUEST_CNTL, 0,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1299

REG_SET(DC_IP_REQUEST_CNTL, 0,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

319

REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

321

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

355

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

477

REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

479

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

536

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

171

REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);

drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

173

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);

drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

222

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

299

REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

301

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

334

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

355

REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

357

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

375

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

471

REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

473

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

497

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

243

REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

245

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

286

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

305

REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

307

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

326

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

133

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

147

REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

149

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

164

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

89

REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

91

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3064

if (REG(DC_IP_REQUEST_CNTL)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3065

REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3067

REG_SET(DC_IP_REQUEST_CNTL, 0,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3080

if (org_ip_request_cntl == 0 && REG(DC_IP_REQUEST_CNTL))

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3081

REG_SET(DC_IP_REQUEST_CNTL, 0,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3156

if (REG(DC_IP_REQUEST_CNTL)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3157

REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3175

if (org_ip_request_cntl == 0 && REG(DC_IP_REQUEST_CNTL))

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3626

if (REG(DC_IP_REQUEST_CNTL))

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3627

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, enable ? 1 : 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3641

if (REG(DC_IP_REQUEST_CNTL))

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3642

REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3653

if (REG(DC_IP_REQUEST_CNTL) && hws->funcs.dpp_pg_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3657

if (REG(DC_IP_REQUEST_CNTL) && hws->funcs.hubp_pg_control)

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

101

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

199

REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

201

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

276

REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

278

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

323

REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

325

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

426

REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

428

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

99

REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

111

PG_CNTL_SF(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh)

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

138

uint32_t DC_IP_REQUEST_CNTL;

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

57

SR(DC_IP_REQUEST_CNTL)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

195

REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

197

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

282

REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

284

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

343

REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

345

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

441

REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

443

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

486

REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

488

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

554

REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

556

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

80

REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

82

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.h

124

PG_CNTL_SF(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.h

181

PG_CNTL_SF(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.h

200

uint32_t DC_IP_REQUEST_CNTL;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.h

37

SR(DC_IP_REQUEST_CNTL)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.h

66

SR(DC_IP_REQUEST_CNTL)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

772

SR(DC_IP_REQUEST_CNTL), \

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

806

HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

781

SR(DC_IP_REQUEST_CNTL), \

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

818

HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

771

SR(DC_IP_REQUEST_CNTL), \

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

805

HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

766

SR(DC_IP_REQUEST_CNTL), \

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

800

HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

625

SR(DC_IP_REQUEST_CNTL), \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

661

HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

615

SR(DC_IP_REQUEST_CNTL), \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

651

HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

633

HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

211

SR(DC_IP_REQUEST_CNTL), \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

613

HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

620

HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.h

67

SR(DC_IP_REQUEST_CNTL), \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

596

SR(DC_IP_REQUEST_CNTL), \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

645

HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

565

SR(DC_IP_REQUEST_CNTL), \

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

618

HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

595

SR(DC_IP_REQUEST_CNTL), \

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

659

HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \