ADVERTISE_1000HALF
mii_giga_ctrl_data |= ADVERTISE_1000HALF;
mii_giga_ctrl_data |= ADVERTISE_1000HALF |
(ADVERTISE_1000FULL | ADVERTISE_1000HALF)
if (advertise & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)
else if (common & ADVERTISE_1000HALF) {
#define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL |
tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
val &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL);
val |= ADVERTISE_1000HALF;
} else if (mscr & ADVERTISE_1000HALF && mssr & LPA_1000HALF) {
adv &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
adv |= ADVERTISE_1000HALF;
mii_1000t_ctrl_reg &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL);
ADVERTISE_1000FULL | ADVERTISE_1000HALF);
mii_control_1000 &= ~ADVERTISE_1000HALF;
else if (val & ADVERTISE_1000HALF)
ctrl1000 |= ADVERTISE_1000HALF;
MII_REG_BITS_OFF(ADVERTISE_1000FULL | ADVERTISE_1000HALF, MII_CTRL1000, vptr->mac_regs);
else if (MII_REG_BITS_IS_ON(ADVERTISE_1000HALF, MII_CTRL1000, regs))
if (MII_REG_BITS_IS_ON(ADVERTISE_1000HALF | ADVERTISE_1000FULL, MII_CTRL1000, regs))
if (MII_REG_BITS_IS_ON(ADVERTISE_1000HALF | ADVERTISE_1000FULL, MII_CTRL1000, regs))
MII_REG_BITS_ON(ADVERTISE_1000FULL | ADVERTISE_1000HALF, MII_CTRL1000, vptr->mac_regs);
CTRL1000 &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
tmp2 = advert2 & ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL);
~(ADVERTISE_1000HALF | ADVERTISE_1000FULL);
ADVERTISE_1000FULL | ADVERTISE_1000HALF,
#define DP83869_CFG1_DEFAULT (ADVERTISE_1000HALF | \
ADVERTISE_1000FULL | ADVERTISE_1000HALF, reg);
ADVERTISE_1000FULL | ADVERTISE_1000HALF,
ADVERTISE_1000FULL | ADVERTISE_1000HALF,
ADVERTISE_1000FULL | ADVERTISE_1000HALF,
ADVERTISE_1000HALF);
result |= ADVERTISE_1000HALF;
result |= ADVERTISE_1000HALF;
if (adv & ADVERTISE_1000HALF)
ctrl1000 & ADVERTISE_1000HALF);