Symbol: DDC_DDCMD0
drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c
121
sif_write_mask(ddc, DDC_DDCMD0, 0xff, 0, (msg->addr << 1) | 0x01);
drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c
171
offset = DDC_DDCMD0;
drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c
193
sif_write_mask(ddc, DDC_DDCMD0, DDCM_DATA0, 0, msg->addr << 1);
drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c
194
sif_write_mask(ddc, DDC_DDCMD0, DDCM_DATA1, 8, msg->buf[0]);