drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

105

sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_SIF_MODE_MASK,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

107

sif_set_bit(ddc, DDC_DDCMCTL1, DDCM_TRI);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

108

readl_poll_timeout(ddc->regs + DDC_DDCMCTL1, val,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

122

sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK, DDCM_PGLEN_OFFSET,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

125

ack = sif_read_mask(ddc, DDC_DDCMCTL1, DDCM_ACK_MASK, DDCM_ACK_OFFSET);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

146

sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

152

ack = sif_read_mask(ddc, DDC_DDCMCTL1, DDCM_ACK_MASK,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

195

sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK, DDCM_PGLEN_OFFSET,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

199

ack = sif_read_mask(ddc, DDC_DDCMCTL1, DDCM_ACK_MASK, DDCM_ACK_OFFSET);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

227

if (sif_bit_is_set(ddc, DDC_DDCMCTL1, DDCM_TRI)) {