drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

102

FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_SEQ_WRITE) |

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

114

regmap_update_bits(ddc->regs, DDC_CTRL, DDC_CTRL_CMD,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

115

FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_ABORT_XFER));

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

140

regmap_update_bits(ddc->regs, DDC_CTRL, DDC_CTRL_CMD,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

141

FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_CLEAR_FIFO));

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

175

FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_ENH_READ_NOACK) |

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

188

FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_SEQ_READ_NOACK) |

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

202

regmap_update_bits(ddc->regs, DDC_CTRL, DDC_CTRL_CMD,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

203

FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_ABORT_XFER));

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

50

regmap_update_bits(ddc->regs, DDC_CTRL, DDC_CTRL_CMD,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

51

FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_CLOCK_SCL));