drivers/gpu/drm/amd/display/dc/dc.h

1815

struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

6229

double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2] = { { 0 } };

drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c

200

unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};

drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c

201

unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0};

drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c

202

unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0};

drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c

203

unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0};

drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c

205

unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200};

drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c

282

while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {

drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c

296

while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {

drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c

301

while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&

drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c

196

unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};

drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c

197

unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0};

drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c

198

unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0};

drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c

199

unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0};

drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c

201

unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200};

drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c

287

while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {

drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c

302

while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {

drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c

307

while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

7033

double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2];

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

7120

double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2812

unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564};

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3155

unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3156

unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0};

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3157

unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0};

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3158

unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0};

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3162

unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564};

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3231

while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3245

while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3250

while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

2984

double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2];

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

2987

for (i = 0; i < DC__VOLTAGE_STATES; ++i) {

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

354

unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564};

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

712

unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

713

unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0};

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

714

unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0};

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

715

unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0};

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

717

unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {615, 906, 1324, 1564};

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

781

while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

795

while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

800

while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&

drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h

182

struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

1034

double UrgentLatencySupportUsPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

1036

double FabricAndDRAMBandwidthPerState[DC__VOLTAGE_STATES];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

1037

bool UrgentLatencySupport[DC__VOLTAGE_STATES][2];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

1038

unsigned int SwathWidthYPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

1039

unsigned int SwathHeightYPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

1088

double PHYCLKD18PerState[DC__VOLTAGE_STATES];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

1097

bool DynamicMetadataSupported[DC__VOLTAGE_STATES][2];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

1105

double UrgLatency[DC__VOLTAGE_STATES];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

1106

double VActiveCursorBandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

1107

double VActivePixelBandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

1108

bool NoTimeForPrefetch[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

1109

bool NoTimeForDynamicMetadata[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

1110

double dpte_row_bandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

1111

double meta_row_bandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

1112

double DETBufferSizeYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

1113

double DETBufferSizeCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

1114

unsigned int swath_width_luma_ub_all_states[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

1115

unsigned int swath_width_chroma_ub_all_states[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

1116

bool NotUrgentLatencyHiding[DC__VOLTAGE_STATES][2];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

1117

unsigned int SwathHeightYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

1118

unsigned int SwathHeightCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

1119

unsigned int SwathWidthYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

1120

unsigned int SwathWidthCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

1121

double TotalDPTERowBandwidth[DC__VOLTAGE_STATES][2];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

1122

double TotalMetaRowBandwidth[DC__VOLTAGE_STATES][2];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

1123

double TotalVActiveCursorBandwidth[DC__VOLTAGE_STATES][2];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

1124

double TotalVActivePixelBandwidth[DC__VOLTAGE_STATES][2];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

1168

bool LinkCapacitySupport[DC__VOLTAGE_STATES];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

1187

unsigned int NotEnoughUrgentLatencyHidingA[DC__VOLTAGE_STATES][2];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

1195

unsigned int TotalNumberOfSingleDPPSurfaces[DC__VOLTAGE_STATES][2];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

1196

unsigned int CompressedBufferSizeInkByteAllStates[DC__VOLTAGE_STATES][2];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

1197

unsigned int DETBufferSizeInKByteAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

1204

enum dm_fclock_change_support FCLKChangeSupport[DC__VOLTAGE_STATES][2];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

1205

bool USRRetrainingSupport[DC__VOLTAGE_STATES][2];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

1207

bool UnboundedRequestEnabledAllStates[DC__VOLTAGE_STATES][2];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

1218

unsigned int RequiredSlots[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

1219

bool ExceededMultistreamSlots[DC__VOLTAGE_STATES];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

1228

bool NotEnoughDSCSlices[DC__VOLTAGE_STATES];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

1229

bool PixelsPerLinePerDSCUnitSupport[DC__VOLTAGE_STATES];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

1230

bool DCCMetaBufferSizeNotExceeded[DC__VOLTAGE_STATES][2];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

1238

bool VActiveBandwithSupport[DC__VOLTAGE_STATES][2];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

1239

bool NotEnoughDETSwathFillLatencyHidingPerState[DC__VOLTAGE_STATES][2];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

317

double ActiveDRAMClockChangeLatencyMarginPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];// DML doesn't save active margin per state

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

536

unsigned int PrefetchMode[DC__VOLTAGE_STATES][2];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

537

unsigned int PrefetchModePerState[DC__VOLTAGE_STATES][2];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

599

double DCFCLKPerState[DC__VOLTAGE_STATES];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

600

double DCFCLKState[DC__VOLTAGE_STATES][2];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

601

double FabricClockPerState[DC__VOLTAGE_STATES];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

602

double SOCCLKPerState[DC__VOLTAGE_STATES];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

603

double PHYCLKPerState[DC__VOLTAGE_STATES];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

604

double DTBCLKPerState[DC__VOLTAGE_STATES];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

605

double MaxDppclk[DC__VOLTAGE_STATES];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

606

double MaxDSCCLK[DC__VOLTAGE_STATES];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

607

double DRAMSpeedPerState[DC__VOLTAGE_STATES];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

608

double MaxDispclk[DC__VOLTAGE_STATES];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

610

double PHYCLKD32PerState[DC__VOLTAGE_STATES];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

620

bool BandwidthSupport[DC__VOLTAGE_STATES];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

624

bool IsErrorResult[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

632

enum dm_validation_status ValidationStatus[DC__VOLTAGE_STATES];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

659

bool use_one_row_for_frame[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

660

bool use_one_row_for_frame_flip[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

664

unsigned int OutputTypeAndRatePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

665

double RequiredDISPCLKPerSurface[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

673

bool ODMCombine2To1SupportCheckOK[DC__VOLTAGE_STATES];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

677

enum dm_output_type OutputTypePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

678

enum dm_output_rate OutputRatePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

695

double MaxMaxVStartup[DC__VOLTAGE_STATES][2];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

722

double ProjectedDCFCLKDeepSleep[DC__VOLTAGE_STATES][2];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

740

double IdealSDPPortBandwidthPerState[DC__VOLTAGE_STATES][2];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

741

unsigned int NoOfDPP[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

743

enum odm_combine_mode ODMCombineEnablePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

745

unsigned int SwathHeightCPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

748

double VRatioPreY[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

749

double VRatioPreC[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

750

double RequiredPrefetchPixelDataBWLuma[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

751

double RequiredPrefetchPixelDataBWChroma[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

752

double RequiredDPPCLK[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

754

bool PTEBufferSizeNotExceededY[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

755

bool PTEBufferSizeNotExceededC[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

756

bool BandwidthWithoutPrefetchSupported[DC__VOLTAGE_STATES][2];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

757

bool PrefetchSupported[DC__VOLTAGE_STATES][2];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

758

bool VRatioInPrefetchSupported[DC__VOLTAGE_STATES][2];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

759

double RequiredDISPCLK[DC__VOLTAGE_STATES][2];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

760

bool DISPCLK_DPPCLK_Support[DC__VOLTAGE_STATES][2];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

761

bool TotalAvailablePipesSupport[DC__VOLTAGE_STATES][2];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

762

unsigned int TotalNumberOfActiveDPP[DC__VOLTAGE_STATES][2];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

763

unsigned int TotalNumberOfDCCActiveDPP[DC__VOLTAGE_STATES][2];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

764

bool ModeSupport[DC__VOLTAGE_STATES][2];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

765

double ReturnBWPerState[DC__VOLTAGE_STATES][2];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

766

bool DIOSupport[DC__VOLTAGE_STATES];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

767

bool NotEnoughDSCUnits[DC__VOLTAGE_STATES];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

768

bool DSCCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

769

bool DTBCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

770

double UrgentRoundTripAndOutOfOrderLatencyPerState[DC__VOLTAGE_STATES];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

771

bool ROBSupport[DC__VOLTAGE_STATES][2];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

773

bool DCCMetaBufferSizeSupport[DC__VOLTAGE_STATES][2];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

774

bool PTEBufferSizeNotExceeded[DC__VOLTAGE_STATES][2];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

775

bool TotalVerticalActiveBandwidthSupport[DC__VOLTAGE_STATES][2];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

776

double MaxTotalVerticalActiveAvailableBandwidth[DC__VOLTAGE_STATES][2];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

778

double PDEAndMetaPTEBytesPerFrame[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

779

double MetaRowBytes[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

780

double DPTEBytesPerRow[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

781

double PrefetchLinesY[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

782

double PrefetchLinesC[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

794

bool RequiresDSC[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

795

unsigned int NumberOfDSCSlice[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

796

double RequiresFEC[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

797

double OutputBppPerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

798

double DSCDelayPerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

799

bool ViewportSizeSupport[DC__VOLTAGE_STATES][2];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

814

double MaximumVStartup[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

826

bool ImmediateFlipSupportedForState[DC__VOLTAGE_STATES][2];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

827

double WritebackDelay[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

847

enum clock_change_support DRAMClockChangeSupport[DC__VOLTAGE_STATES][2];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

856

bool MPCCombine[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

888

unsigned int TotalNumberOfSingleDPPPlanes[DC__VOLTAGE_STATES][2];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

890

bool ODMCombine4To1SupportCheckOK[DC__VOLTAGE_STATES];

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

897

unsigned int NotEnoughUrgentLatencyHiding[DC__VOLTAGE_STATES][2];

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2136

unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2137

unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0};

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2138

unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0};

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2139

unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0};

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2141

unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200};

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2227

while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2241

while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2246

while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&